Principal Firmware Engineer - Austin, United States
Originally posted 13 July 2026 by the employer.
Develop bare-metal firmware for DDR5 PHY microcontrollers within the Cadence DDR PHY IP Front End Design team.
About the role
Cadence is seeking a Principal Firmware Engineer for the DDR PHY IP Front End Design team in Austin. The role focuses on developing firmware for DDR5 PHY using microcontrollers and bare-metal C programming.
What you'll do
- Develop firmware for DDR5 PHY using microcontrollers. - Develop firmware in C involving bare-metal programming and low-level APIs on microcontrollers. - Collaborate with hardware designers and memory subsystem architects to derive and implement training algorithms. - Collaborate with the verification team to deduce firmware-hardware co-verification plans. - Develop and debug firmware in RTL-based hardware simulations (C + Verilog simulations). - Develop and debug on silicon bring-up boards.
What you'll need
- Knowledge of the DDR5 JEDEC spec and knowledge of different DIMM configurations and specifications. - Experience developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks. - Knowledge of C programming language for embedded software development and use of relevant IDE. - Experience debugging RTL simulations involving firmware and microcontroller subsystems. - Knowledge of Shell, Perl, Python, or TCL scripting. - Experience with verification EDA tools such as simulators and waveform viewers.
Skills: firmware for DDR5 PHY, bare-metal programming, low-level APIs, training algorithms, firmware-hardware co-verification