Principal Ethernet Scale-Out Architect, AI Data Center - Santa Clara, California, United States of America
$192,000 - $304,900 USD yearly
Originally posted 13 August 2026 by the employer.
About the role
This role is responsible for architecting large-scale Ethernet-based AI/datacenter fabrics that connect servers, accelerators, racks, and multi-rack clusters. The selected candidate will drive system architecture and requirements from the accelerator card and server level through rack and cluster-scale deployments.
What you'll do
- Develop end-to-end system architecture spanning accelerator cards, servers, racks, and multi-rack clusters.
- Drive architecture and requirements for Ethernet fabrics, NICs/SuperNICs, switch ASICs, transport protocols, in-network collectives, telemetry, security, virtualization, RAS, and reliability features.
- Analyze DMA engines, data flows, packet flows, and system bottlenecks to optimize bandwidth, latency, utilization, and scalability.
- Collaborate with software, SoC design, card design, platform, and validation teams to realize connectivity solutions for AI scale-up and scale-out deployments.
- Provide technical leadership across physical, link, transaction, transport, and protocol layers of high-speed interfaces and datacenter networking systems.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
- 8 years of hardware architecture, design, validation, testing, or commercialization experience in datacenter, networking, accelerator, or high-speed I/O products.
- Strong understanding of Ethernet, InfiniBand, RoCEv2, RDMA, and related transport protocols.
- 3 years of experience with datacenter products such as servers, accelerators, NICs, switches, racks, or cluster-scale systems.
- Strong knowledge of scale-out networking and scale-up interconnect architectures for AI and cloud infrastructure.
- In-depth knowledge of Ethernet, high-speed SerDes, PCIe/CXL-class interfaces, and board/system-level connectivity tradeoffs.
- Strong understanding of telemetry, observability, RAS, reliability, error handling, and failure-mode analysis in large-scale systems.
- Strong understanding of security, isolation, virtualization, and multi-tenant deployment requirements in datacenter environments.
- Strong understanding of DMA engines, memory hierarchy, I/O virtualization, and accelerator data-movement architectures.
Nice to have
- Good understanding of PCIe, CXL, and UCIe protocols and their use in accelerator, server, and rack-scale architectures.
- Familiarity with Ethernet switch management and control-plane ecosystems such as SONiC, SAI, OpenBMC, Linux networking, and related platform software.
- Good understanding of high-speed SerDes and Ethernet PHY design considerations, including signal integrity, reach, power, latency, and platform tradeoffs.
- Ability to work with customers, product management, architecture, and engineering teams to gather requirements and translate them into clear technical specifications.
Skills: scale-out network architectures, AI and cloud datacenter, Ethernet fabrics, NICs/SuperNICs, transport protocols
This role has been open 65 days — well below the 78-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
474
|
Median days open
78 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (474 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 73 | 474 |
| Open roles in the wider Digital Design & Verification family | 381 | 3202 · 115 employers |
| Median days open | 87 d | 78 d (+9 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: scale-out network architectures, AI and cloud datacenter, Ethernet fabrics, NICs/SuperNICs, transport protocols
Who's hiring in this category
- Qualcomm (this employer) · 75 open roles · median 85 d
- NVIDIA · 56 open roles · median 70 d
- Apple · 36 open roles · median 11 d
- AMD · 34 open roles · median 59 d
- Arm Holdings · 27 open roles · median 114 d
- Micron Technology · 22 open roles · median 106 d
How we counted: 474 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.