Principal Engineer - Verification - AZ - Chandler, United States
Originally posted 6 October 2026 by the employer.
Join our dsPIC Business Unit to lead IP-level verification using formal verification and UVM testbenches.
About the role
As a Principal Engineer, you will lead IP-level verification for dsPIC products, utilizing formal verification and UVM testbenches.
What you'll do
- Architect, develop, and maintain UVM and Formal verification environments.
- Define verification plans and implement constrained-random UVM Testbench and/or Formal Testbench.
- Develop assertions and coverage in System Verilog language, analyze coverage metrics, and drive coverage closure.
- Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and architecture teams to resolve defects.
- Collaborate with SoC development teams to integrate IP-level testbenches and tests into SoC-level verification environments.
- Provide technical support and mentoring to verification engineers.
What you'll need
- 10+ years of experience in functional verification.
- Strong expertise in SystemVerilog language, assertions, and UVM methodology.
- Proven experience building IP-level and SoC-level verification environments using UVM and/or formal verification Testbenches.
- Understanding of digital design, RTL fundamentals, and ARM/RISC SoC architectures.
- Strong communication, teamwork, and problem-solving skills.
Nice to have
- Demonstrated success in mentoring engineers and leading verification efforts across global teams.
- Experience driving methodology improvements and automation initiatives.
Skills: UVM, SystemVerilog, formal verification, IP-level verification, coverage closure
This role has been open 3 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1206
|
Median days open
63 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (1206 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 1206 |
| Open roles in the wider Digital Design & Verification family | 68 | 3175 · 113 employers |
| Median days open | 61 d | 63 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM, SystemVerilog, formal verification, IP-level verification, coverage closure
Who's hiring in this category
- Qualcomm · 111 open roles · median 42 d
- AMD · 102 open roles · median 49 d
- NVIDIA · 76 open roles · median 62 d
- Synopsys · 61 open roles · median 25 d
- SiFive · 55 open roles · median 66 d
- Micron Technology · 52 open roles · median 98 d
How we counted: 1206 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.