Principal Engineer - Validation Engineering - San Jose, California, United States
$185,000 - $240,000 USD yearly
Originally posted 30 September 2026 by the employer.
About the role
It involves turning complex silicon, board, and system requirements into rigorous plans, scalable automation, and clear release decisions, specifically for CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
What you'll do
- Define validation methodologies, coverage goals, schedules, dependencies, and exit criteria for hardware and connectivity products.
- Translate product requirements and architecture specifications into validation plans, test cases, and measurable quality objectives.
- Lead silicon, board, and system bring-up, including test environment definition, instrumentation selection, configuration, and execution.
- Architect scalable lab infrastructure and automated test frameworks.
- Develop, review, and maintain Python-based automation and data analysis tools in Linux-based validation environments.
- Drive root-cause analysis of functional, performance, interoperability, reliability, and system-level issues across hardware, firmware, and software boundaries.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 8-12 years of experience in hardware, silicon, system, or product validation engineering.
- Proven experience leading validation for semiconductor, networking, connectivity, or data center products.
- Hands-on experience creating validation plans, test cases, automation, coverage metrics, and release criteria.
- Strong debugging skills across hardware, firmware, software, and laboratory instrumentation.
- Excellent written and verbal communication skills.
Nice to have
- Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience validating high-speed connectivity interfaces such as PCIe, CXL, Ethernet, or comparable technologies.
- Understanding of physical-layer fundamentals, signal integrity, protocol analysis, compliance, and interoperability testing.
- Proficiency with Python, Linux, laboratory equipment, data analysis, and Microsoft Azure DevOps or comparable validation infrastructure.
- Experience scaling validation labs, working with hyperscalers or ODMs, and mentoring engineers.
Skills: validation strategies, silicon bring-up, test automation, root-cause analysis, PCIe/CXL/Ethernet
This role has been open 0 days — well below the 46-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
362
|
Median days open
46 d
|
Median salary
$170k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (362 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 362 |
| Open roles in the wider Silicon Validation & Test family | 19 | 2168 · 109 employers |
| Median days open | 180 d | 46 d (+134 d vs this employer) |
| Median salary (USD postings) | — | $170k |
Skills observed across this category: validation strategies, silicon bring-up, test automation, root-cause analysis, PCIe/CXL/Ethernet
Who's hiring in this category
- AMD · 57 open roles · median 51 d
- Micron Technology · 35 open roles · median 27 d
- Qualcomm · 24 open roles · median 89 d
- NVIDIA · 21 open roles · median 26 d
- Graphcore · 18 open roles · median 102 d
- Microchip Technology · 17 open roles · median 58 d
How we counted: 362 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.