Principal Engineer, Test Engineering - USA - San Diego, CA, United States
$137,000 - $196,000 USD yearly
Originally posted 6 August 2026 by the employer.
Architect comprehensive test solutions for mixed-signal products covering sensing applications in wearables, cell phones, industrial, and automotive.
About the role
As a Principal Engineer, Test Engineering, you will serve as the technical authority and strategic leader for new product introduction test development in Semtech's mixed-signal product portfolio. This role involves architecting comprehensive test solutions spanning from early silicon validation through high-volume production for sensing products.
What you'll do
- Architect and define test strategies for complex mixed-signal products from concept through production.
- Drive DFT/testability requirements into IC architecture, establishing company-wide standards and best practices.
- Develop and implement advanced test techniques for sensing products.
- Lead test readiness reviews with stakeholders, providing strategic recommendations.
- Interface with customer quality teams on test specifications and coverage requirements.
- Ensure seamless transfer of test solutions to high-volume OSATs.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
- 12+ years of progressive experience in semiconductor test engineering.
- 8+ years specifically in mixed-signal test development.
- Expert-level proficiency with Advantest V93000 platform (SmarTest 7/8).
- Advanced programming skills in C/C++, Python, and TCL.
- Deep understanding of high-speed signal integrity, jitter analysis, and BER testing.
- Expertise in analog/mixed-signal DFT techniques (BIST, scan, boundary scan).
- Strong foundation in statistical process control and quality methodologies.
- Experience with PCB design tools (Cadence, Altium) and signal integrity simulation.
Nice to have
- Master's degree or PhD in relevant engineering discipline.
- 15+ years in semiconductor test.
- Experience with SiGe BiCMOS process technology and its test challenges.
- Knowledge of automotive quality standards (AEC-Q100) and qualification flows.
- Familiarity with 93000 PS1600/PS3600 digital channels and Wave Scale RF.
- Experience with wafer-level testing and probe card design.
- Experience with test data analytics and machine learning applications.
This role has been open 73 days — well above the 30-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
551
|
Median days open
30 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Semtech | All employers we track in this specialty (551 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 551 |
| Open roles in the wider Silicon Validation & Test family | 25 | 2219 · 113 employers |
| Median days open | 73 d | 30 d (+43 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Who's hiring in this category
- Teradyne · 75 open roles · median 24 d
- Renesas Electronics · 43 open roles · median 24 d
- Infineon Technologies · 41 open roles · median 40 d
- Micron Technology · 29 open roles · median 34 d
- Qualcomm · 28 open roles · median 30 d
- Texas Instruments · 23 open roles · median 25 d
How we counted: 551 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.