Principal Engineer, Signal Integrity - Santa Clara, CA, United States
$150,680 - $225,700 USD yearly
Originally posted 15 October 2026 by the employer.
About the role
This role drives execution across highly complex, cross-functional programs addressing some of the most demanding challenges in AI, wired and wireless communications, and critical infrastructure markets. This role is responsible for definition, analysis, and verification of the system interconnect for high-speed digital systems across board, switch, and optical platforms.
What you'll do
- Interface with circuit design, applications engineering, packaging technology, and board/switch design teams to define and implement system interconnect.
- Own deliverables including timing assessment, bump/RDL and package ballout specifications, and reference routing guidelines.
- Lead signal integrity delivery simulations using SI/PI tools, and conduct lab debug and measurement to correlate simulation results.
- Develop SI/PI methodologies, rules, and workflows to meet platform-level specifications across high-speed traces and critical power domains.
- Own required steps supporting SI/PI including package and PCB model generation, analysis, simulation, measurement, and correlation.
- Proactively identify signal integrity risks across the platform stack, develop mitigation strategies, and escalate issues as needed to drive resolution.
What you'll need
- Bachelor's degree in Electrical Engineering or related field and 10-15 years of related professional experience; Master's degree and/or PhD in Electrical Engineering or related field with 5-10 years of experience.
- Strong understanding of EM fundamentals, transmission line theory, via structures, high-speed connectors, and complex BGA packages.
- Proficiency in 2D/3D EM simulation tools such as HFSS, Q3D, Sigrity Suite, or ADS, as well as HSPICE.
- Experience with lab equipment such as oscilloscopes, network analyzers, and TDR.
- Hands-on experience across board, switch, and optics platforms, including high-speed PCB layout, package technology, and optical module/interconnect integration.
- Familiarity with high-speed interfaces such as DDR, PCIe, SerDes (25Gbps, 112G and 224G PAM4), USB, SATA, or other high-speed parallel/serial buses.
Nice to have
- Experience setting up, running, and summarizing power integrity simulations is a plus.
Skills: signal integrity, system interconnect, package ballout, SI/PI tools, high-speed interfaces, DDR, PCIe, SerDes
This role has been open 1 day — well below the 112-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · Serdes Highspeed
|
Open roles in category
87
|
Median days open
112 d
|
Median salary
$199k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (87 roles · 35 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 87 |
| Open roles in the wider Software, Firmware & Systems family | 72 | 6157 · 145 employers |
| Median days open | 186 d | 112 d (+74 d vs this employer) |
| Median salary (USD postings) | — | $199k |
Skills observed across this category: signal integrity, system interconnect, package ballout, SI/PI tools, high-speed interfaces, DDR
Who's hiring in this category
- NVIDIA · 15 open roles · median 59 d
- Qualcomm · 10 open roles · median 190 d
- AMD · 5 open roles · median 122 d
- Keysight Technologies · 4 open roles · median 143 d
- Broadcom · 3 open roles · median 200 d
- Intel Corporation · 3 open roles · median 3 d
How we counted: 87 open Hardware Systems Engineering (Serdes Highspeed) roles from 35 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.