Principal Engineer - Signal Integrity - Boise, ID - Main Site, United States
Originally posted 6 October 2026 by the employer.
About the role
What you'll do
- Lead the development and analysis of high-speed memory interfaces and power distribution networks.
- Drive and develop SI/PI aspects of future standards (JEDEC, ONFI, and IBIS) through system and product electrical capability exploration.
- Formulate techniques and protocols for SI/PI analysis.
- Support and drive path-finding activities for IO and channel innovation.
- Represent the Signal Integrity R&D team in technical cross-functional collaborative groups.
What you'll need
- PhD or MSEE, or equivalent experience, with at least 5 years of industry experience.
- Deep experience in Signal and Power Integrity, particularly in areas affecting I/O circuit signaling performance, PMICs, current workloads, PI performance & optimization.
- Required courses covering electromagnetic, transmission line and RF theory, and analog build or similar fields.
- Experience with E.M. field solvers (quasi-static and full wave), time and frequency domain simulation tools like Q3D, SIWAVE, HFSS, POWERSI, CLARITY, HSPICE, ADS.
- Deep understanding of electromagnetic and transmission line theory, general I/O build, signal integrity, differential and single-ended interface technologies.
- Expertise in Printed Circuit Board (PCB) layout or electrical package development techniques.
- Experience in building and analyzing high-speed single-ended or differential buses.
- Familiarity with lab measurement equipment like Oscilloscopes, TDR, Vector Network Analyzer (VNA).
Nice to have
- Familiarity with peak distortion analysis, statistical analysis (DOE), and equivalent tools (JMP).
- Memory industry experience.
- Understanding of AI/ML.
Skills: high speed memory interfaces, power distribution networks, Signal and Power Integrity, E.M. field solvers, lab measurement equipment
This role has been open 9 days — well below the 70-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
238
|
Median days open
70 d
|
Median salary
$182k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (238 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 14 | 238 |
| Open roles in the wider Analog & Mixed-Signal family | 48 | 1423 · 106 employers |
| Median days open | 54 d | 70 d (−16 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Skills observed across this category: high speed memory interfaces, power distribution networks, Signal and Power Integrity, E.M. field solvers, lab measurement equipment
Who's hiring in this category
- Synopsys · 31 open roles · median 31 d
- AMD · 29 open roles · median 37 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 170 d
- Micron Technology (this employer) · 14 open roles · median 54 d
- Apple · 12 open roles · median 17 d
How we counted: 238 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.