Principal Engineer – Physical Design - AZ - Chandler, United States
Originally posted 14 May 2026 by the employer. Relisted by the employer on 22 June 2026.
Work on Full Chip APR and Netlist-to-GDSII physical implementation for hierarchical, low power, multi-mode mixed signal designs.
About the role
Microchip’s CAD Physical Design (PD) team is looking for a Principal Engineer to work on Full Chip APR/Physical Implementation (Netlist-to-GDSII). You will work as part of a worldwide team on physical implementation including APR of hierarchical, low power, multi-mode, multi corner mixed signal designs.
What you'll do
- Execute Netlist-to-GDSII physical implementation across hierarchical, low power, multi-mode, and multi-corner mixed signal designs. - Drive all aspects of physical design flows including floor planning, placement optimization, clock tree synthesis, routing, crosstalk avoidance, and physical verification. - Lead full chip physical design activities and apply advanced place and route methodologies. - Deliver design timing closure using advanced VLSI logic principles and clock structures. - Run sign-off tools for Static Timing Analysis, Formal Equivalence, Parasitic Extraction, Power Integrity, and Physical Verification. - Implement UPF and low power design practices throughout the entire physical design flow using Tcl and Perl scripting.
What you'll need
- Bachelor’s or Master's degree in Electrical / Electronics Engineering with 10+ years of relevant experience. - Hands-on experience across physical design flows including floor planning, placement optimization, clock tree synthesis, routing, crosstalk avoidance, and physical verification. - Recent experience leading full chip Physical Design activities. - Advanced knowledge of sign-off tools for Static Timing Analysis, Formal Equivalence, Parasitic Extraction, Power Integrity, and Physical Verification. - Knowledge and hands-on experience with UPF and low power design practices throughout the physical design flow. - Experience with 40nm or 28nm technologies. - Proficiency in Tcl and Perl scripting.
Nice to have
- Daily use of ICC/ICC2 or Innovus. - Experience with 16nm or smaller technology.
Skills: physical design, floor planning, placement optimization, clock tree synthesis, routing, physical verification, STA, UPF, ICC/ICC2, Innovus
This role has been open 222 days — well above the 182-day median for Physical Design roles.
Physical Design · Digital Backend
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Open roles in category
37
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Median days open
182 d
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Median salary
—
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (37 roles · 21 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 37 |
| Open roles in the wider Physical Implementation family | 28 | 1505 · 111 employers |
| Median days open | 222 d | 182 d (+40 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: physical design, floor planning, placement optimization, clock tree synthesis, routing, physical verification
Who's hiring in this category
- Micron Technology · 4 open roles · median 126 d
- Qualcomm · 4 open roles · median 105 d
- Intel Corporation · 3 open roles · median 18 d
- SiTime · 3 open roles · median 95 d
- Altera · 2 open roles · median 222 d
- Analog Devices · 2 open roles · median 208 d
How we counted: 37 open Physical Design (Digital Backend) roles from 21 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.