Principal Engineer / MTS, PDE Package Design - MSB, Singapore

Originally posted 7 October 2026 by the employer.

About the role

This role involves owning package architecture and execution from feasibility through tape-out, qualification, and production readiness. The Principal Engineer/MTS will serve as the technical authority for complex package issues and integrate floorplan, interface, interconnect, power, signal, thermal, and mechanical requirements into silicon-package-board co-design.

What you'll do

• Own package architecture and execution from feasibility through tape-out, qualification, and production readiness.
• Serve as the technical authority for complex package issues, leading cross-functional reviews and trade-off decisions.
• Advance design rules, methodologies, automation workflows, and technology roadmaps.
• Represent the packaging team in silicon-package-board co-design.
• Apply digital fluency and AI literacy to use AI-enabled tools for research, analysis, and problem-solving.

What you'll need

• Master’s degree in Electrical Engineering, Mechanical Engineering, Materials Engineering, or a related discipline.
• Minimum 10 years of relevant experience with deep expertise in package architecture and silicon-package co-design.
• Hands-on experience with multiple relevant package technologies and strong knowledge of manufacturability, assembly processes, substrates, materials, reliability, and failure mechanisms.
• Proven ownership of complex package designs from feasibility and trade-off studies through NPI tape-out, qualification, and manufacturing handoff.
• Advanced proficiency with Cadence Allegro Package Designer / SiP Layout or equivalent package-design tools, including design-rule and review workflows.
• Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness.

Skills: package architecture, silicon-package co-design, substrate layout, routing, Cadence Allegro Package Designer