Principal Engineer - HIG HBM - ARCHITECTURE - Richardson, TX, United States
Originally posted 15 September 2026 by the employer.
About the role
This role defines and drives the architecture of high-speed analog and mixed-signal IO subsystems for High Bandwidth Memory (HBM) products.
What you'll do
- Define and drive HBM PHY and IO architecture, balancing performance, power, area, reliability, and manufacturability.
- Architect high-performance transmit and receive paths, including clocking, signaling, equalization, timing alignment, and interface optimization.
- Define and optimize analog calibration architectures, including impedance calibration, reference voltage calibration, timing calibration, and adaptive tuning methodologies.
- Develop and maintain IO timing budgets, design targets, and margin methodologies across process, voltage, temperature, and package variations.
- Influence future HBM roadmap decisions and develop engineering methodologies.
- Mentor design teams on architectural principles, calibration strategies, and best practices for high-speed IO design.
What you'll need
- MS or PhD in Electrical Engineering or a related field.
- 7+ years of experience in semiconductor design, architecture, or technology development.
- Demonstrated expertise in analog and mixed-signal IO design and architecture.
- Deep knowledge of high-speed transmitter, receiver, clocking, and timing architectures.
- Strong technical communication and documentation skills.
Nice to have
- Experience with HBM, DDR, UCIe, PCIe, or other high-speed memory and interconnect technologies.
- Experience developing and evaluating analog calibration schemes, including impedance calibration, reference voltage calibration, timing calibration, adaptive and background calibration techniques.
- Experience with advanced packaging technologies, including 2.5D, 3D integration, and TSV-based systems.
- Background in clock generation, clock distribution, PLLs, phase alignment, or timing recovery circuits.
- Experience with silicon bring-up, product engineering, or post-silicon debug.
- Demonstrated use of AI-enabled analytics or automation techniques to improve design quality, silicon analysis, or engineering productivity.
- Experience developing design methodologies, architecture standards, and engineering training material.
- Strong understanding of simulation, modeling, silicon characterization, and simulation-to-silicon correlation.
- Proven ability to perform architectural tradeoff analysis across performance, power, area, and reliability constraints.
Skills: HBM architecture, PHY and IO architecture, analog calibration architectures, IO timing budgets, high-speed IO design, 2.5D/3D integration
This role has been open 19 days — well below the 75-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
442
|
Median days open
75 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (442 roles · 64 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 442 |
| Open roles in the wider Digital Design & Verification family | 103 | 3109 · 114 employers |
| Median days open | 121 d | 75 d (+46 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: HBM architecture, PHY and IO architecture, analog calibration architectures, IO timing budgets, high-speed IO design, 2.5D/3D integration
Who's hiring in this category
- Qualcomm · 71 open roles · median 82 d
- NVIDIA · 57 open roles · median 59 d
- AMD · 36 open roles · median 61 d
- Arm Holdings · 27 open roles · median 102 d
- Renesas Electronics · 22 open roles · median 59 d
- NXP Semiconductors · 20 open roles · median 104 d
How we counted: 442 open SoC/Chip Architecture (SOC Architecture) roles from 64 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.