Principal Engineer, Hardware Design (AI2518) - San Jose, California, United States
$203,800 - $315,900 USD yearly
Originally posted 18 June 2026 by the employer.
About the role
This role owns complex design blocks from microarchitecture definition and RTL implementation through verification support and silicon bring-up.
What you'll do
- Own microarchitecture definition and RTL implementation of complex blocks from concept through silicon. - Drive ground-up block design from specification and microarchitecture to RTL, integration, and bring-up. - Develop synthesizable RTL using Verilog and SystemVerilog, including custom logic, protocol adaptation, and data-path optimizations. - Define block-level interfaces, microarchitectural trade-offs, and design specifications. - Collaborate with verification, physical design, architecture, and firmware teams to meet functional, timing, power, and area targets. - Drive block-level synthesis, timing closure, and DFT readiness.
What you'll need
- Master's degree in Electrical Engineering, Computer Engineering, or related field. - 10+ years of experience in ASIC design, with a focus on block-level RTL design and silicon development. - Proven track record of ground-up block design, taking blocks from microarchitecture and RTL through to working silicon. - Expert-level RTL design skills in Verilog/SystemVerilog, with hands-on experience in synthesis, timing closure, and DFT concepts. - Understanding of microarchitecture trade-offs, data-path and control logic design, and block-level optimization for power, performance, and area. - Experience with post-silicon validation and debug using lab equipment such as oscilloscopes, logic analyzers, and protocol analyzers.
Nice to have
- Experience designing hardware for machine learning / AI accelerators. - Experience integrating blocks into larger SoCs. - Experience implementing or integrating high-speed interfaces such as PCIe and UCIe. - Exposure to firmware or driver development for high-speed interfaces.
Skills: RTL design, ground-up block-level silicon development, microarchitecture, Verilog/SystemVerilog, synthesis
This role has been open 111 days — well above the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1051
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiMa.ai | All employers we track in this specialty (1051 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1051 |
| Open roles in the wider Digital Design & Verification family | 11 | 3283 · 116 employers |
| Median days open | 14 d | 62 d (−48 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL design, ground-up block-level silicon development, microarchitecture, Verilog/SystemVerilog, synthesis
Who's hiring in this category
- Qualcomm · 150 open roles · median 57 d
- Synopsys · 84 open roles · median 35 d
- AMD · 72 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 89 d
- NVIDIA · 40 open roles · median 62 d
How we counted: 1051 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.