Principal Engineer DSP PHY Digital Design - Dallas TX (United States), United States
Originally posted 5 June 2026 by the employer.
About the role
As a Principal Engineer DSP PHY Digital Design in the Research & Development team, you will architect and simulate DSP signal chains for automotive Ethernet PHYs, defining features, performance targets, and algorithm specifications for mixed-signal and digital teams.
What you'll do
- Develop equalization and adaptation algorithms for wireline channels, including FFE/DFE, adaptive filtering, and fixed-point considerations. - Design and implement timing recovery and synchronization blocks such as CDR and tracking loops, managing jitter tolerance and stability/latency tradeoffs. - Contribute to detection and coding/FEC integration, including soft-information interfaces, performance/complexity tradeoffs, and link KPIs. - Build bit-true and fixed-point models and reference implementations primarily in C++ and MATLAB. - Define verification metrics and stress tests covering BER/FER, convergence time, and corner cases, partnering with DV to ensure coverage. - Support silicon bring-up and lab debug by correlating models with silicon, root-causing issues, and iterating on algorithms and specs.
What you'll need
- B.S. + 10 years (or M.S. + 7 years) in Electrical Engineering, Computer Engineering, or a related field. - Strong fundamentals in digital communications and DSP, including probability and statistics. - Practical experience in high-speed wireline DSP, including a mix of FFE/DFE, adaptation, CDR, MLSD/Viterbi concepts, FEC integration, and fixed-point modeling. - Strong C++ and MATLAB skills for algorithm development, modeling, and analysis.
Nice to have
- Experience with automotive Ethernet PHY/SerDes constraints, including robustness, low latency, interoperability, and EMI resilience. - Familiarity with ADC-based receiver architectures and calibration concepts. - Experience translating algorithms into RTL-friendly specs, including throughput/latency budgeting, memory/compute sizing, and state-machine behavior. - Knowledge of link startup/training/autoneg concepts and system validation. - Exposure to standards work such as IEEE 802.3 or cross-company technical leadership.
This role has been open 162 days — well above the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1084
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (1084 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 1084 |
| Open roles in the wider Digital Design & Verification family | 90 | 3328 · 115 employers |
| Median days open | 60 d | 63 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 160 open roles · median 60 d
- Synopsys · 87 open roles · median 36 d
- AMD · 77 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 92 d
- NVIDIA · 39 open roles · median 64 d
How we counted: 1084 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.