Principal Engineer DSP Design - Dallas TX (United States), United States
Originally posted 5 June 2026 by the employer.
Architect and implement DSP signal chains for automotive Ethernet PHYs from fixed-point models to silicon bring-up.
About the role
As a Principal Engineer DSP Design in the Research & Development team, you will architect and simulate DSP signal chains for automotive Ethernet PHYs. You will translate algorithms and fixed-point models into synthesizable hardware implementations and support post-silicon validation.
What you'll do
- Architect and simulate DSP signal chains for automotive Ethernet PHYs, defining features, performance targets, and algorithm specifications for mixed-signal and digital teams. - Implement DSP algorithms including filtering, error correction coding, echo cancellation, and receiver equalization in Verilog/System Verilog. - Translate fixed-point MATLAB/C/C++ models into fixed-point, synthesizable HDL code in collaboration with algorithm and systems teams. - Perform RTL design and implement timing recovery/synchronization blocks such as CDR and tracking loops, managing jitter tolerance, stability, and latency tradeoffs. - Contribute to detection and coding / FEC integration, addressing soft-information interfaces, performance/complexity tradeoffs, and link KPIs. - Support silicon bring-up and lab debug by correlating model to silicon behavior, root-causing issues, and iterating on algorithms and specifications.
What you'll need
- B.S. + 10 years (or M.S. + 7 years) in Electrical Engineering, Computer Engineering, or a related field. - Strong fundamentals in digital communications and DSP, including probability and statistics. - Practical experience in high-speed wireline DSP, covering areas such as FFE/DFE, adaptation, CDR, MLSD/Viterbi concepts, FEC integration, and fixed-point modeling. - Strong C++ and MATLAB skills for algorithm development, modeling, and analysis.
Skills: DSP signal chains, automotive Ethernet PHYs, Verilog/System Verilog, fixed-point MATLAB/C/C++ models, timing recovery/synchronization, FEC, silicon bring-up
This role has been open 162 days — well above the 95-day median for Digital/RTL Design roles.
Digital/RTL Design · Mixed Signal DSP
|
Open roles in category
32
|
Median days open
95 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (32 roles · 17 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 32 |
| Open roles in the wider Digital Design & Verification family | 90 | 3328 · 115 employers |
| Median days open | 48 d | 95 d (−47 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: DSP signal chains, automotive Ethernet PHYs, Verilog/System Verilog, fixed-point MATLAB/C/C++ models, timing recovery/synchronization, FEC
Who's hiring in this category
- Celero · 5 open roles · median 2 d
- Infineon Technologies (this employer) · 4 open roles · median 48 d
- Keysight Technologies · 4 open roles · median 116 d
- Altera · 2 open roles · median 34 d
- Marvell Technology · 2 open roles · median 154 d
- NXP Semiconductors · 2 open roles · median 123 d
How we counted: 32 open Digital/RTL Design (Mixed Signal DSP) roles from 17 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.