Principal Engineer, Digital IC Design and Architecture - United States
$157,080 - $227,460 USD yearly
Originally posted 15 July 2026 by the employer — open 57 days.
Join our Automotive OpenGMSL Team as a Principal Engineer, Digital IC Design and Architecture.
About the role
This role involves leading the architecture and design of complex high-speed SerDes ICs for automotive systems. This technology enables the reliable transport of multi-Gigabit high-speed video, sensor, and control data across vehicle networks, and is also applied in industrial automation, medical imaging, and robotics.
What you'll do
- Architect and design digital blocks and subsystems for complex high-speed SerDes ICs, including Gigabit-speed serial interfaces.
- Drive the evolution of OpenGMSL technology through new architectures and authoring OpenGMSL technical standards.
- Use Verilog and SystemVerilog for RTL design of digital blocks, subsystems, and top-level designs.
- Develop block-level testbenches, verify block functionality, and collaborate on full-chip verification and coverage closure.
- Perform block- and top-level linting, CDC analysis, and power analysis, assisting with synthesis constraints and timing closure.
- Support silicon bring-up, characterization, and debug activities.
What you'll need
- Master's degree in Electrical Engineering or equivalent with 7+ years of relevant experience or PhD with 4+ years of relevant experience.
- Experience designing and verifying complex digital systems using Verilog/SystemVerilog.
- Demonstrated ability to architect and plan designs at the system level, translating high-level product concepts into robust design implementations.
- Understanding of communication theory, high-speed SerDes transceiver architectures, and video/data transport.
- Solid understanding of digital and analog design trade-offs, with experience in timing analysis, power estimation, physical design, and DFT concepts.
- Hands-on experience with silicon bring-up and debug.
Nice to have
- Expertise in high-speed SerDes standards and protocols, including Ethernet, USB, PCIe, and/or video (DisplayPort, CSI/DSI, HDMI).
- Experience authoring SerDes technical standards and/or participating in industry standards committees.
- Experience with behavioral modeling, including verification of mixed-signal systems with behavioral modeling.
- Proficiency in Matlab and design of DSP blocks, including digital filters and signal-processing algorithms.
- Experience leading teams and/or projects.
Skills: SerDes, Gigabit serial interfaces, RTL Design, SystemVerilog, silicon bring-up
This role has been open 56 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Analog Devices | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 4 | 217 |
| Median days open | 92 d | 91 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SerDes, Gigabit serial interfaces, RTL Design, SystemVerilog, silicon bring-up
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.