Principal Engineer Digital Design - Irvine
$175,300 - $241,000 USD yearly
Originally posted 8 April 2026 by the employer.
About the role
As a Principal Engineer Digital Design in the Research & Development team, you will implement DSP algorithms and define hardware architectures in Verilog and System Verilog.
What you'll do
- Implement DSP algorithms including Filtering, Error Correction coding, Echo Cancellation, and Receiver Equalization in Verilog and System Verilog. - Collaborate with algorithm and systems teams to define hardware architecture. - Translate fixed-point MATLAB, C, and C++ models into fixed-point, synthesizable HDL code. - Conduct performance analysis, optimizing for latency, throughput, power, and area (PPA). - Perform linting and CDC checks to ensure high-quality design hand-off, and collaborate with the DV team to verify functionality. - Support FPGA/ASIC synthesis, timing closure, and silicon debugging.
What you'll need
- Bachelor’s or Master’s degree in EE or Computer Engineering. - 12+ years of experience in RTL design using Verilog or System Verilog. - Experience with EDA tools such as Synopsys Design Compiler or Cadence.
Skills: DSP algorithms, Verilog/System Verilog, hardware architecture, fixed-point HDL, PPA optimization
This role has been open 200 days — well above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1083
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (1083 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 1083 |
| Open roles in the wider Digital Design & Verification family | 90 | 3310 · 115 employers |
| Median days open | 61 d | 64 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: DSP algorithms, Verilog/System Verilog, hardware architecture, fixed-point HDL, PPA optimization
Who's hiring in this category
- Qualcomm · 160 open roles · median 61 d
- Synopsys · 87 open roles · median 37 d
- AMD · 77 open roles · median 43 d
- Analog Devices · 49 open roles · median 54 d
- NXP Semiconductors · 42 open roles · median 93 d
- NVIDIA · 40 open roles · median 64 d
How we counted: 1083 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.