Principal Engineer Design - Bangalore BTP
Originally posted 13 August 2026 by the employer.
About the role
This role involves the end-to-end design and development of IO libraries, ensuring their integration into subsystems and compliance with defined specifications.
What you'll do
- Own end-to-end IO library design and development.
- Collaborate with system architects to define and finalize IO specifications.
- Lead IO integration into subsystems and provide expert guidance on IO selection, implementation, and qualification.
- Define IO architectures and align designs with product requirements.
- Mentor and review team members' work to improve design quality, performance, power, and area optimization.
- Provide hands-on support for Front-End (FE) and Back-End (BE) development activities.
What you'll need
- 12+ years of IO design and development experience.
- Expertise in IO design for LVTTL, LVCMOS, DDR, SPI, xSPI, Oscillator, LVDS, and voltage-tolerant circuits.
- Understanding of ESD (Electrostatic Discharge) and Latch-Up concepts.
- Experience with IO library characterization methodologies.
- Proven ability to lead small design/layout teams and drive architecture development and project planning.
- Track record of delivering chip designs from specification to silicon.
Skills: IO library design, IO specifications, LVTTL, LVCMOS, DDR, SPI, ESD
This role has been open 47 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 67 | 1385 · 107 employers |
| Median days open | 95 d | 76 d (+19 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: IO library design, IO specifications, LVTTL, LVCMOS, DDR, SPI
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.