Principal Engineer, CE CAD - Richardson, TX, United States
Originally posted 8 June 2026 by the employer.
About the role
As a Memory Design Group CAD Engineer, you will evaluate, develop, enhance, and debug in-house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout and design of CMOS integrated circuits.
What you'll do
- Develop tools, flows, and methodologies to increase the productivity and reliability of memory designs. - Integrate commercial EDA tools into design flows and identify deficiencies in current tools and flows. - Provide training, documentation, and support to end users across design, layout, verification, and process teams. - Undertake independent research and development of CAD software to meet product development needs. - Evaluate tools with internal customers and define flows for improvement of efficiency and cost. - Develop, maintain, and support the engineering infrastructure.
What you'll need
- Strong programming fundamentals with experience in Unix and shell scripting. - Knowledge of CMOS circuits, deep-submicron physical design, CMOS manufacturing, and layout design rules. - Experience with layout flows including Calibre DRC/LVS, floorplanning, automated P&R, and SPF extraction. - Experience with design simulation tools and languages including Verilog, Verilog-A, ncverilog, VCS, Spice/FastSpice, FineSim/PrimeSim, and HSPICE. - Experience with RTL-to-GDS flows and Agentic AI.
Nice to have
- Experience with Cadence Virtuoso DFII and SKILL programming. - Proficiency with Python and Python Qt frameworks. - Bachelor’s or Master’s degree in CE/EE/EECS with 5+ years of industry experience.
Skills: EDA tools, design flows, Cadence Virtuoso, Calibre DRC/LVS, Verilog
This role has been open 174 days — well above the 70-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
704
|
Median days open
70 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (704 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 45 | 704 |
| Open roles in the wider Physical Implementation family | 77 | 1513 · 111 employers |
| Median days open | 55 d | 70 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: EDA tools, design flows, Cadence Virtuoso, Calibre DRC/LVS, Verilog
Who's hiring in this category
- Cadence Design Systems · 156 open roles · median 153 d
- Synopsys · 63 open roles · median 45 d
- Micron Technology (this employer) · 45 open roles · median 55 d
- GlobalFoundries · 40 open roles · median 28 d
- Qualcomm · 39 open roles · median 78 d
- Keysight Technologies · 35 open roles · median 60 d
How we counted: 704 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.