Principal Engineer - CAD (Physical Verification) - AZ - Chandler, United States
Originally posted 26 August 2026 by the employer.
About the role
This role focuses on flow development and support for back-end physical verification within the CAD group, providing innovative solutions for the design community.
What you'll do
- Develop physical verification regression test cases to QA physical verification decks
- Support Layout and Design engineers with physical verification activities using tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules
- Utilize knowledge of advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, via doubling methodologies
- Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design for manufacturability checks
- Develop and verify rule decks to support flow and enhance foundry rule decks
- Support remote sites worldwide with layout verification activities and debug physical verification issues
- Develop flows to improve quality and reliability of devices
What you'll need
- Bachelors in Electrical Engineering or related field with 10 years of experience developing and supporting physical verification activities
- In-depth knowledge of Calibre DesignRev scripting
- Fluent with SVRF and TVF
- Accomplished at debugging PV issues with RVE, Vue, or other EDA visualizer
- Familiar with customizing Calibre Interactive
- Skilled with Tcl/Tk, Perl, Python, and other programming languages, inside and outside of EDA tools
- Solid knowledge of layout rules and concepts, device identification concepts, and foundry rules
- Strong knowledge of Design for Manufacturing solutions affecting quality, reliability, and yield of designs
- Extensive knowledge of Calibre, Pegasus, Hercules syntax and semantics, or similar layout verification tool
- Strong knowledge of Cadence Virtuoso and/or CalibreDRV
Nice to have
- Masters in Electrical Engineering or related field
- Extraction, Reliability, and Dynamic Noise related knowledge
Skills: physical verification, Calibre, Pegasus, DRC, LVS, PDK
This role has been open 50 days — well below the 78-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
688
|
Median days open
78 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (688 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 688 |
| Open roles in the wider Physical Implementation family | 28 | 1459 · 108 employers |
| Median days open | 42 d | 78 d (−36 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: physical verification, Calibre, Pegasus, DRC, LVS, PDK
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 168 d
- Synopsys · 65 open roles · median 38 d
- Micron Technology · 44 open roles · median 80 d
- Qualcomm · 41 open roles · median 66 d
- NVIDIA · 39 open roles · median 79 d
- GlobalFoundries · 33 open roles · median 35 d
How we counted: 688 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.