Principal Engineer – CAD Design Engineering & EDA Infrastructure - San Jose, CA, United States
$248,400 USD yearly
Originally posted 22 June 2026 by the employer.
About the role
The Principal Engineer – CAD Design Engineering & EDA Infrastructure leads the strategy, architecture, development, and operational execution of CAD and EDA environments supporting ASIC, SoC, IP, and verification teams.
What you'll do
- Define and execute the roadmap and architecture for CAD and EDA infrastructure, including hybrid compute environments and cloud-enabled workflows. - Optimize RTL-to-GDSII design flows across synthesis, place-and-route, STA, DFT, verification, emulation, and signoff. - Evaluate, deploy, and maintain EDA tools from vendors including Synopsys, Cadence, and Siemens/Mentor. - Architect and manage Linux-based compute farms, distributed job scheduling systems, HPC clusters, storage, and networking. - Drive automation, self-service monitoring dashboards, and CI/CD practices using Python, Tcl, Perl, and Shell scripting. - Manage EDA license infrastructure, capacity planning, and utilization optimization across engineering environments.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline. - 12+ years of experience in semiconductor design methodologies, CAD engineering, or EDA infrastructure. - Deep understanding of ASIC/SoC design and verification flows. - Hands-on experience with EDA platforms from Synopsys and Cadence EDA. - Strong expertise with Linux/Unix environments, distributed computing systems, and managing large-scale compute farms, license servers, and storage systems. - Advanced programming and automation skills in Python, Tcl, Shell, or similar languages.
Skills: EDA methodologies, design automation, RTL-to-GDSII, compute farms, AI/ML-driven flows, license management
This role has been open 89 days — well above the 74-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
671
|
Median days open
74 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lattice Semiconductor | All employers we track in this specialty (671 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 671 |
| Open roles in the wider Physical Implementation family | 7 | 1441 · 109 employers |
| Median days open | 89 d | 74 d (+15 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: EDA methodologies, design automation, RTL-to-GDSII, compute farms, AI/ML-driven flows, license management
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 171 d
- Synopsys · 63 open roles · median 37 d
- Micron Technology · 44 open roles · median 48 d
- Qualcomm · 36 open roles · median 76 d
- GlobalFoundries · 33 open roles · median 39 d
- Keysight Technologies · 32 open roles · median 73 d
How we counted: 671 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.