Principal Engineer, ATE Test Development Engineer - Santa Clara, CA, United States
Originally posted 22 September 2026 by the employer.
Advantest 93000 platform testing for high-speed SerDes operating above 112 Gbps in MCM, CPC, and CPO architectures.
About the role
The Principal Engineer, ATE Test Development Engineer provides technical leadership in the architecture and scalability of Automated Test Equipment (ATE) test solutions for hyperscale devices. The position oversees ATE test program development across wafer sort, final test, and system-level test on the Advantest 93000 platform.
What you'll do
- Define and own the end-to-end test strategy across wafer sort, final test, production, and system-level test (SLT) on the Advantest 93000 platform. - Lead ATE test solution development, silicon bring-up, bench validation, correlation to simulation, and first-silicon debug for new tape-outs. - Design and develop high-speed ATE hardware supporting data rates above 112 Gbps for semiconductor products. - Collaborate with DFT, DFM, and design teams to review testability, evaluate coverage, and convert design-level test content into ATE-ready patterns. - Drive test flow optimization, test time reduction, yield improvement, and test program transfer to OSAT and foundry test floors. - Support customer returns (RMA), including debug of customer-reported silicon issues and test escape investigations.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related discipline. - 5 to 10 years of experience in semiconductor test engineering with complex SoC, ASIC, or analog test programs. - Hands-on experience with Advantest 93000 ATE platforms and SmarTest-8 test program development. - Deep understanding of DFT techniques including scan, BIST, boundary scan/JTAG, ATPG, SSN, and test coverage analysis. - Experience with high-speed SerDes, high-power ATE testing, and test hardware design for data rates exceeding 112 Gbps. - Proficiency in scripting test automation and data analysis using Java, C/C++, Perl, or Python. - Track record of building scalable ATE test libraries and methods for MCM, CPC, and CPO product lines.
This role has been open 30 days — below the 34-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
562
|
Median days open
34 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (562 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 562 |
| Open roles in the wider Silicon Validation & Test family | 59 | 2256 · 113 employers |
| Median days open | 30 d | 34 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Who's hiring in this category
- Teradyne · 81 open roles · median 26 d
- Infineon Technologies · 45 open roles · median 41 d
- Renesas Electronics · 45 open roles · median 27 d
- Micron Technology · 28 open roles · median 38 d
- Qualcomm · 28 open roles · median 34 d
- Texas Instruments · 25 open roles · median 29 d
How we counted: 562 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.