Principal Engineer - ASIC Digital Design (Memory Interface IP- HBM/DDR/LPDDR)
Originally posted 13 September 2026 by the employer.
Work on memory interface IP for AI accelerators, data centers, and high-performance compute.
About the role
This role involves designing and owning complex RTL blocks for memory interface IP. The work focuses on HBM, DDR, and LPDDR architectures for AI accelerators, data centers, and high-performance compute applications.
What you'll do
- Design and own complex RTL blocks for HBM, DDR, and LPDDR memory interface IP from architecture through implementation and verification handoff.
- Collaborate with analog design teams to define and validate mixed-signal interfaces, ensuring timing closure and signal integrity.
- Develop and execute detailed verification plans, including corner case analysis and protocol compliance testing.
- Drive timing, power, and area optimization using EDA tools like Synopsys Fusion Compiler, PrimeTime, and DC Compiler.
- Lead technical reviews and design audits, providing direction on architecture tradeoffs and implementation risks.
- Mentor engineers, reviewing RTL code and guiding design decisions.
- Interface with customer engineering teams to debug integration issues and ensure successful IP deployment.
What you'll need
- 8-10+ years of hands-on ASIC digital design experience with a focus on RTL design and verification.
- Expertise in at least two of the following memory interface protocols: HBM, DDR4, DDR5, LPDDR4, LPDDR5.
- Proven experience designing and delivering production-quality IP or SoC blocks that have taped out and been validated in silicon.
- Strong command of SystemVerilog for RTL design and familiarity with UVM or other verification methodologies.
- Experience working with AMBA protocols (AXI, AHB, APB) in the context of memory subsystem integration.
- Proficiency with Synopsys or Cadence EDA toolchains for synthesis, timing analysis, and power optimization.
This role has been open 20 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
968
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (968 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 68 | 968 |
| Open roles in the wider Digital Design & Verification family | 152 | 3109 · 114 employers |
| Median days open | 25 d | 62 d (−37 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 139 open roles · median 59 d
- Synopsys (this employer) · 68 open roles · median 25 d
- AMD · 64 open roles · median 45 d
- NXP Semiconductors · 47 open roles · median 81 d
- Analog Devices · 45 open roles · median 40 d
- NVIDIA · 45 open roles · median 59 d
How we counted: 968 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.