Principal Engineer, Architecture & Performance Research for Data Center and Agentic AI CPU
$219,000 - $351,000 USD yearly
Originally posted 2 October 2026 by the employer.
About the role
This role focuses on researching CPU microarchitecture and performance for emerging computing workloads, specifically in data center and agentic AI. The work involves exploring new architectural ideas, evaluating their performance potential, and rapidly turning concepts into designs validated on silicon.
What you'll do
- Lead end-to-end performance analysis using architectural simulators and RTL to guide architectural trade-offs.
- Translate workload characterization and performance insights into architectural requirements and long-term design direction.
- Drive architecture-to-implementation alignment with design teams, ensuring architectural intent is carried through RTL and silicon.
- Mentor Senior and Staff engineers and provide technical leadership across multiple projects and architectural domains.
- Drive research and technical contributions leading to patents and publications.
What you'll need
- Master’s degree in Computer Engineering, Computer Science, or a related field with 18+ years of relevant experience, or PhD with 15+ years of relevant experience.
- 5+ years of experience in CPU microarchitecture, architecture research, or performance engineering.
- Extensive experience designing and evaluating high-performance CPU architectures, including RISC-V, ARM, or x86 cores; experience with GPU/NPU vector or accelerator architectures is also relevant.
- Proven ability to use quantitative performance analysis and modeling to identify architectural opportunities and evaluate system-level trade-offs.
- Deep expertise in at least one major microarchitectural domain: Front-end (Branch prediction, fetch/decode, instruction delivery, decoupled front-end architectures), Mid-end (Out-of-order execution, scheduling, RVV/SIMD, vector execution, matrix/tensor acceleration), or Back-end (Load/store units, MSHRs, cache and memory systems, prefetching, irregular memory access optimization).
- Hands-on experience building, extending, and applying architectural simulators and performance models, such as gem5.
- Strong programming skills in C/C++ and Python, with experience developing tools and automation for performance analysis and architectural exploration.
- Demonstrated ability to take architectural concepts from research and modeling through RTL implementation and silicon validation.
Nice to have
- Experience defining or influencing CPU architecture for emerging workloads, particularly AI/ML, agentic AI, or data center applications.
- Experience with AI-driven architecture and design methodologies, including AI-assisted architecture exploration, high-level design, or RTL generation.
- Strong perspective on memory-centric architectures and CPU-memory co-design, with experience translating memory-system characteristics into CPU architectural opportunities.
- Experience driving system-level PPA trade-offs across performance, power, area, and implementation complexity.
- Experience taking architectural concepts through RTL implementation, tape-out, and silicon validation.
- Experience leading cross-functional architecture initiatives and influencing technical direction across multiple engineering teams.
- Proven ability to mentor and develop senior technical engineers and shape architecture research across multiple domains.
- Track record of impactful architectural innovation through patents, publications, or deployed products.
Skills: CPU architecture, microarchitectural innovation, performance models, AI-driven methodologies, memory-centric architectures
This role has been open 7 days — well below the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
461
|
Median days open
76 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (461 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 461 |
| Open roles in the wider Digital Design & Verification family | 14 | 3183 · 114 employers |
| Median days open | 40 d | 76 d (−36 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: CPU architecture, microarchitectural innovation, performance models, AI-driven methodologies, memory-centric architectures
Who's hiring in this category
- Qualcomm · 77 open roles · median 79 d
- NVIDIA · 60 open roles · median 63 d
- AMD · 36 open roles · median 58 d
- Apple · 32 open roles · median 3 d
- Arm Holdings · 27 open roles · median 106 d
- NXP Semiconductors · 21 open roles · median 108 d
How we counted: 461 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.