Principal Engineer - Analog Design (IP Tech Lead) - United States
$75,000 - $232,000 USD yearly
Originally posted 29 July 2026 by the employer — open 43 days.
This role focuses on key analog and mixed-signal building blocks such as high-speed SERDES, PLLs, PVT sensors, IOs.
About the role
This role involves end-to-end technical leadership of mixed-signal IPs, including IP licensing, integration, and silicon validation support, across advanced SoC projects. The focus is on critical analog and mixed-signal building blocks like high-speed SERDES, PLLs, PVT sensors, and IOs, developed using CMOS and FinFET processes.
What you'll do
- Define and review mixed-signal IP interface specifications, integration guidelines, and verification plans.
- Lead the evaluation, selection, and licensing of third-party and internally developed IPs for SoC projects.
- Architect and drive the integration of mixed-signal IPs into SoC designs.
- Review and sign off system level clocking needs to meet electrical compliance.
- Collaborate with design, verification, physical design, and test engineering teams to resolve integration and validation issues.
- Oversee and participate in silicon validation, characterization, and debug of mixed-signal IPs post-fabrication.
What you'll need
- Bachelor's degree in electrical engineering or related field with strong analog/mixed-signal background and at least 10 years of experience in analog/mixed-signal IP design, integration, and validation for SoC applications, or a Master's degree with at least 7.5 years of such experience.
- Strong understanding of SoC architecture, digital-analog interfaces, and system-level integration challenges.
- Proven expertise in PLLs, high-speed SERDES, PVT sensors, and IOs.
- Familiarity with industry-standard EDA tools for design, simulation, and verification.
- Understanding of device physics and basic ESD/Latch-up concepts.
Nice to have
- Experience working with PCIe, SAS, SATA and Ethernet protocols.
- Experience working with Chiplet technologies.
Skills: analog/mixed-signal IPs, high-speed SERDES, PLLs, SoC architecture, silicon validation
This role has been open 79 days — exactly the 79-day median for Mixed-Signal Design roles.
Mixed-Signal Design · Mixed Signal
|
Open roles in category
173
|
Median days open
79 d
|
Median salary
$178k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (173 roles · 44 employers) |
|---|---|---|
| Open roles in category | 8 | 173 |
| Median days open | 168 d | 79 d (+89 d vs this employer) |
| Median salary (USD postings) | — | $178k |
Skills observed across this category: analog/mixed-signal IPs, high-speed SERDES, PLLs, SoC architecture, silicon validation
Who's hiring in this category
- Analog Devices · 25 open roles · median 117 d
- Infineon Technologies · 14 open roles · median 71 d
- NVIDIA · 12 open roles · median 51 d
- SiTime · 11 open roles · median 169 d
- Qualcomm · 10 open roles · median 55 d
- Microchip Technology (this employer) · 8 open roles · median 168 d
How we counted: 173 open Mixed-Signal Design (Mixed Signal) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.