Principal Engineer - Analog Design - India

Originally posted 5 August 2026 by the employer — open 36 days. Relisted by the employer on 5 August 2026.

Design analog IP blocks including multi-GHz PLL circuits and high speed digital circuits.

About the role

This role involves the design, simulation, and validation of analog integrated circuits (ICs) for mixed-signal SOC designs. You will be part of the Analog IP team, developing critical IP blocks used in Timing and Communication Group (TCG) timing products.

What you'll do

• Work with analog design leads and architects to design specific analog IP blocks.
• Simulate analog circuits across process corners and operating conditions.
• Develop models of design blocks for inclusion in top-level mixed-signal simulations.
• Perform block-level validation of silicon process devices and system-level laboratory evaluation.

What you'll need

• Master’s degree or PhD in electrical engineering.
• Minimum 5 years of direct experience working on analog and mixed-signal circuits.
• High-speed and analog circuit design experience including ADCs, DACs, Filters, PLLs, DLLs, and high-speed I/Os.
• Strong fundamentals in circuit theory, design, and layout.
• Hands-on experience in scripting and automation using skill language, python, Perl, and tcl.
• Strong knowledge in Cadence IC design flow and tools.
• Strong knowledgeable in Verilog-A for analog behavioral modeling and simulation.

Nice to have

• Expertise in the system design of mixed signal circuits.

Skills: analog IP, deep sub-micron process, Ultra Low Power High Speed Analog Mixed Signals, Power Management, ADC, DAC, Cadence tools