Principal Engineer, AI & ML Design Verification (AI2517) - San Jose, California, United States
$203,800 - $315,900 USD yearly
Originally posted 18 June 2026 by the employer.
Functional verification and UVM testbench architecture for Machine Learning Accelerator (MLA) IP.
About the role
The Principal Engineer, AI & ML Design Verification executes and closes functional verification for Machine Learning Accelerator (MLA) and data processing logic at the block, sub-system, and SoC levels. The role also develops, enhances, and maintains MLA testbenches and test cases, while supporting bring-up and debugging on emulators and silicon.
What you'll do
- Independently perform MLA verification execution and closure. - Participate in MLA architecture, micro-architecture, and feature discussions and reviews. - Define and develop MLA test bench components using UVM and System Verilog. - Develop and execute test plans, lead code coverage reviews and closure, and develop System Verilog Assertion functional coverage. - Manage debugging of test and regression failures, and assist the emulation team with triaging failures. - Work closely with Architecture, SoC Hardware, and Software teams.
What you'll need
- BS or MS in Electrical Engineering or Computer Science with 12+ years of experience in functional verification of pipeline-based designs such as MLAs, DSPs, CPUs, or GPUs. - Extensive experience with UVM and System Verilog based verification methodology. - Proven experience developing UVM and System Verilog testbenches (including BFMs, ScoreBoards, and SVA) from scratch, along with debug and coverage tools. - Strong knowledge of AMBA protocols. - Solid debugging, coding, and problem-solving skills.
Nice to have
- Silicon debug skills on lab and board setups. - Formal/SVA knowledge.
Skills: MLA Design Verification, UVM, System Verilog, test plans, functional verification
This role has been open 111 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1220
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiMa.ai | All employers we track in this specialty (1220 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1220 |
| Open roles in the wider Digital Design & Verification family | 11 | 3283 · 116 employers |
| Median days open | 111 d | 64 d (+47 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: MLA Design Verification, UVM, System Verilog, test plans, functional verification
Who's hiring in this category
- Qualcomm · 114 open roles · median 41 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 62 d
- Synopsys · 65 open roles · median 36 d
- SiFive · 55 open roles · median 78 d
- Cadence Design Systems · 50 open roles · median 120 d
How we counted: 1220 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.