Principal Emulation Engineer - San Jose, California, United States
$138,000 - $206,000 USD yearly
Originally posted 19 August 2026 by the employer.
This role focuses on large-scale hardware emulation and FPGA prototyping for memory-centric computing SoCs.
About the role
This role involves building and maintaining large-scale hardware emulation and FPGA prototyping platforms for memory-centric computing SoCs, enabling pre-silicon hardware and software validation. You will work on solving complex system-level challenges posed by AI/ML workloads.
What you'll do
- Build, bring up, and maintain large-scale hardware emulation and FPGA prototyping platforms for memory-centric computing SoCs.
- Partition and map complex multi-million-gate designs onto emulation systems and multi-FPGA prototypes.
- Develop transactors, speed bridges, and co-emulation (SCE-MI) environments.
- Model memory subsystems, clock and reset schemes, and high-speed I/O interfaces.
- Enable early firmware, driver, and software bring-up by delivering stable emulation and prototype targets.
- Debug complex hardware and software issues using waveform capture, assertions, and coverage.
What you'll need
- 20+ years of industry experience with a Bachelor's, 18+ years with a Master's, or 15+ years with a PhD.
- Strong background in pre-silicon verification, validation, and SoC bring-up.
- 5+ years of experience in both FPGA prototyping and large-scale hardware emulation of complex ASIC/SoC designs.
- Hands-on experience with large-scale emulation platforms such as Cadence Palladium, Synopsys ZeBu, or Siemens Veloce.
- Hands-on experience with FPGA prototyping platforms such as Synopsys HAPS or Cadence Protium, including multi-FPGA design partitioning and timing closure.
- Experience with transactors, co-emulation (SCE-MI), speed bridges, and standard interface protocols such as PCIe, DDR/HBM, AXI/CHI, or Ethernet.
- Proficiency in Verilog/SystemVerilog and in design bring-up, clocking, reset, and memory modeling for emulation and prototyping.
- Proficiency in scripting (Tcl, Python, or Perl) for emulation and prototyping flow automation.
- Experience running AI/ML workloads or system-level software pre-silicon.
Nice to have
- Familiarity with agentic AI tools and frameworks.
Skills: hardware emulation, FPGA prototyping, pre-silicon validation, memory-centric computing SoCs, AI/ML workloads
This role has been open 58 days — below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1195
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (1195 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1195 |
| Open roles in the wider Digital Design & Verification family | 13 | 3198 · 115 employers |
| Median days open | 155 d | 64 d (+91 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: hardware emulation, FPGA prototyping, pre-silicon validation, memory-centric computing SoCs, AI/ML workloads
Who's hiring in this category
- Qualcomm · 109 open roles · median 37 d
- AMD · 97 open roles · median 51 d
- NVIDIA · 84 open roles · median 58 d
- Synopsys · 63 open roles · median 31 d
- SiFive · 55 open roles · median 73 d
- Arm Holdings · 49 open roles · median 101 d
How we counted: 1195 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.