Principal Digital Verification Engineer - Chandler (Office), United States
Originally posted 12 August 2026 by the employer.
Verify PMIC digital control.
About the role
What you'll do
- Lead digital verification activities and drive project execution from planning through signoff.
- Define verification plans, methodologies, environments, regressions, coverage goals, and signoff criteria.
- Develop and maintain advanced verification environments using SystemVerilog, UVM, VIPs, scoreboards, monitors, checkers, and assertions.
- Create directed and constrained-random test scenarios to validate functionality, performance, robustness, and corner-case behavior.
- Define, implement, and analyze functional, code, and assertion coverage; drive coverage closure and signoff.
- Verify PMIC digital control, telemetry, diagnostics, safety, power sequencing, fault management, and communication interfaces.
What you'll need
- BSEE with 8+ years, MSEE with 5+ years, or PhD with 3+ years of semiconductor industry experience.
- Strong understanding of digital design fundamentals, FSMs, CDC, reset architecture, low-power design, and SoC integration.
- Expertise in Verilog, SystemVerilog, UVM/OVM, and class-based verification methodologies.
- Strong knowledge of constrained-random, coverage-driven verification, regression automation, and verification signoff.
- Hands-on experience developing testbenches, drivers, monitors, scoreboards, assertions, and reusable verification IP.
- Experience with SystemVerilog Assertions (SVA) and formal verification techniques.
- Knowledge of industry-standard protocols including AMBA, I²C, SPI, UART, CAN, LIN, DDR, and PCIe.
- Proficiency in Python, Perl, and UNIX/Linux shell scripting for automation.
Nice to have
- Familiarity with FPGA, emulation, or prototyping platforms such as HAPS, Palladium, or Zebu.
- Understanding of PMIC architectures and power management concepts.
- Experience using AI/LLM-based technologies to improve engineering productivity.
Skills: SystemVerilog, UVM, constrained-random, coverage closure, PMIC digital control
This role has been open 66 days — slightly above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1205
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (1205 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 42 | 1205 |
| Open roles in the wider Digital Design & Verification family | 128 | 3202 · 115 employers |
| Median days open | 95 d | 64 d (+31 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: SystemVerilog, UVM, constrained-random, coverage closure, PMIC digital control
Who's hiring in this category
- Qualcomm · 110 open roles · median 38 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 86 open roles · median 58 d
- Synopsys · 64 open roles · median 32 d
- SiFive · 55 open roles · median 74 d
- Cadence Design Systems · 50 open roles · median 116 d
How we counted: 1205 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.