Principal Digital Design Engineer - San Jose, California, United States
$185,000 USD yearly
Originally posted 5 October 2026 by the employer.
Design high-performance network controllers for rack-scale AI infrastructure utilizing PCIe, UALink, Esun, and Ethernet protocols.
About the role
This role involves the micro-architecture and implementation of front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high-performance network controllers.
What you'll do
- Develop micro-architecture and implementation of front-end circuit designs.
- Perform RTL, synthesis, IP integration, and block-level verification.
- Drive multiple complex designs to production from architecture to GDS.
- Utilize Synopsys and/or Cadence digital design tools and flows.
- Perform silicon bring-up and debug.
- Implement design for test (DFT), stuck-at and transition scan tests.
What you'll need
- 8+ years of experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking, Server, and/or Storage applications.
- Thorough knowledge of high-speed protocols such as PCIe, UALink, Esun, and Ethernet.
- Proven front-end design expertise including architecture, RTL, simulations, synthesis, timing closure, and GLS.
- Full chip or block level ownership.
- Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
- Experience with small-geometry CMOS (≤28nm) design.
Nice to have
- Firmware development with C-language.
- Scripting with Python or other equivalent programming languages.
- Development/support for PCIe or Ethernet Switch products.
- Familiarity with UVM based design verification.
This role has been open 2 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1006
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1006 roles · 98 employers) |
|---|---|---|
| Open roles in this specialty | 30 | 1006 |
| Open roles in the wider Digital Design & Verification family | 62 | 3184 · 113 employers |
| Median days open | 28 d | 62 d (−34 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 142 open roles · median 62 d
- Synopsys · 82 open roles · median 23 d
- AMD · 74 open roles · median 38 d
- Analog Devices · 48 open roles · median 39 d
- NXP Semiconductors · 48 open roles · median 76 d
- NVIDIA · 46 open roles · median 62 d
How we counted: 1006 open Digital/RTL Design (RTL Design) roles from 98 employers tracked in the SemiconductorJobs index, counted 8 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.