Principal Digital Design Engineer - San Jose, California, United States
$185,000 USD yearly
Originally posted 26 May 2026 by the employer. Relisted by the employer on 14 September 2026.
About the role
Astera Labs is looking for a Principal Digital Design Engineer to develop micro-architecture and drive front-end circuit design for high performance network controllers. The role covers RTL development, synthesis, IP integration, and block-level verification across protocols including PCIe, UALink, and Ethernet.
What you'll do
- Define micro-architecture and implement front-end design, including RTL, synthesis, IP integration, and block-level verification for network controllers. - Drive full chip or block level ownership from architecture to GDS, delivering complex designs to production. - Execute front end design flows including simulation, synthesis, timing closure, gate-level simulation (GLS), and DFT. - Perform stuck-at and transition scan test insertion for design for test (DFT). - Support UVM-based design verification and lead silicon bring-up and debug activities.
What you'll need
- Bachelor's degree in Electrical Engineering. - 8+ years of experience supporting or developing complex SoC/silicon products for Switch ASIC, networking applications, server, or storage. - Hands-on technical knowledge of high-speed protocols including PCIe (Gen-3 and above), UALink, Esun, and Ethernet. - Experience with Synopsys and/or Cadence digital design tools and flows. - Hands-on experience with small-geometry CMOS (≤28nm) design, timing closure, and silicon bring-up. - Familiarity with UVM-based design verification.
Nice to have
- Firmware development experience in C-language and scripting with Python or equivalent programming languages. - Direct experience developing or supporting PCIe or Ethernet Switch products. - Master's degree in Electrical Engineering.
This role has been open 150 days — well above the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1084
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1084 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 1084 |
| Open roles in the wider Digital Design & Verification family | 59 | 3328 · 115 employers |
| Median days open | 43 d | 63 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 160 open roles · median 60 d
- Synopsys · 87 open roles · median 36 d
- AMD · 77 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 92 d
- NVIDIA · 39 open roles · median 64 d
How we counted: 1084 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.