Principal Digital Design Engineer
$185,000 CAD yearly
Originally posted 14 September 2026 by the employer. Relisted by the employer on 2 November 2026.
About the role
Principal Digital Design Engineers develop micro-architecture and front-end circuit design implementations, covering RTL, synthesis, IP integration, and block-level verification for high performance network controllers.
What you'll do
- Develop micro-architecture and front-end circuit designs, including RTL development, synthesis, IP integration, and block-level verification.
- Take full chip or block level ownership from architecture to GDS, driving complex designs to production.
- Execute front end design flows including simulations, synthesis, timing closure, gate-level simulations (GLS), and design for test (DFT).
- Manage DFT implementation, including stuck-at and transition scan test insertion.
- Support silicon bring-up and debug activities.
What you'll need
- Bachelor’s degree in Electrical Engineering.
- 8+ years of experience supporting or developing complex SoC/silicon products for Switch ASIC, networking applications, server, or storage.
- Hands-on knowledge of high-speed protocols including PCIe (Gen-3 and above), UALink, Esun, or Ethernet.
- Experience with Synopsys and/or Cadence digital design tools and flows.
- Experience with small-geometry CMOS (≤28nm) design.
- Familiarity with UVM-based design verification.
Nice to have
- Master’s degree in Electrical Engineering.
- Firmware development with C-language, or scripting with Python or other equivalent programming languages.
- Development or support experience for PCIe or Ethernet Switch products.
More semiconductor jobs: Astera Labs jobs · RTL design jobs · San Jose jobs
This role has been open 48 days — well below the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1057
|
Median days open
60 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1057 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 1057 |
| Open roles in the wider Digital Design & Verification family | 63 | 3376 · 114 employers |
| Median days open | 49 d | 60 d (−11 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 139 open roles · median 69 d
- Synopsys · 85 open roles · median 46 d
- AMD · 81 open roles · median 47 d
- NXP Semiconductors · 44 open roles · median 101 d
- Analog Devices · 42 open roles · median 48 d
- NVIDIA · 41 open roles · median 69 d
How we counted: 1057 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 2 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.