Principal Die-to-Die Interconnect Modeling Architect - United States
$167,500 - $268,000 USD yearly
Originally posted 8 October 2026 by the employer.
About the role
This role involves leading a technical team to build and evolve a foundational modeling platform for die-to-die (D2D) PHYs designs.
What you'll do
- Develop comprehensive behavioral and architectural models that predict complete link behavior before implementation.
- Build system-level models using MATLAB, Python, SystemC, or equivalent modeling environments.
- Predict link performance including BER, latency, throughput, bandwidth density, power consumption, energy efficiency, and manufacturing margin.
- Define the architectural verification strategy to ensure system requirements are traceable from concept through production silicon.
- Drive correlation between behavioral models, RTL simulation, laboratory characterization, and production silicon.
- Provide technical leadership across architecture, analog, digital, firmware, packaging, signal integrity, verification, validation, and product engineering organizations.
What you'll need
- MS in Electrical Engineering, Computer Engineering, and 15 or more years in related field experience; or PhD in Electrical Engineering, Computer Engineering, and 12 or more years in related field experience.
- Deep understanding of communication theory, equalization, and adaptive algorithms.
- Experience in high-speed SerDes, or D2D communication systems architecture.
- Extensive experience developing behavioral and architectural models using MATLAB, Python, SystemC, or equivalent tools.
- Experience with architecture model to RTL to verification.
- Experience leading architectural verification, silicon correlation, and performance validation across multidisciplinary engineering teams.
Nice to have
- Demonstrated expertise in D2D, UCIe, or other short-reach die-to-die communication.
- Expertise in advanced packaging including silicon interposers, EMIB, hybrid bonding, and 3D integration.
- Management experience.
Skills: die-to-die, D2D PHYs, communication theory, system-level modeling, architectural verification, silicon correlation
This role has been open 2 days — well below the 78-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
242
|
Median days open
78 d
|
Median salary
$176k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (242 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 242 |
| Open roles in the wider Analog & Mixed-Signal family | 35 | 1413 · 106 employers |
| Median days open | 81 d | 78 d (+3 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Skills observed across this category: die-to-die, D2D PHYs, communication theory, system-level modeling, architectural verification, silicon correlation
Who's hiring in this category
- AMD · 30 open roles · median 38 d
- Synopsys · 29 open roles · median 26 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 19 open roles · median 184 d
- Micron Technology · 13 open roles · median 71 d
- Apple · 12 open roles · median 12 d
How we counted: 242 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.