Principal DFT Engineer - Irvine, California, United States
$230,000 - $275,000 USD yearly
Originally posted 16 September 2026 by the employer.
About the role
This role involves implementing robust Design-for-Test methodologies that enable high quality, high volume production of complex ASIC and SoC products.
What you'll do
- Develop and implement DFT architecture for ASIC and SoC designs.
- Perform scan insertion, scan chain planning, and scan compression implementation.
- Generate and validate ATPG patterns and analyze fault coverage results.
- Implement and verify MBIST and other on-chip test features.
- Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
- Support JTAG and boundary-scan implementation and debug.
- Drive DFT signoff activities and manufacturing test readiness.
- Participate in silicon bring-up, failure analysis, and yield improvement efforts.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
- 8+ years of ASIC/SoC DFT experience.
- Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
- Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
- Knowledge of Verilog/SystemVerilog and digital design fundamentals.
- Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
- Strong debugging abilities.
Nice to have
- Experience with advanced-node semiconductor technologies.
- Hands-on experience with MBIST, compression architectures, and JTAG.
- Knowledge of timing closure, physical design impacts, and low-power design techniques.
- Experience supporting silicon validation and manufacturing production ramps.
This role has been open 22 days — well below the 54-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
246
|
Median days open
54 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Celero | All employers we track in this specialty (246 roles · 52 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 246 |
| Open roles in the wider Digital Design & Verification family | 5 | 3195 · 113 employers |
| Median days open | 22 d | 54 d (−32 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Who's hiring in this category
- AMD · 40 open roles · median 36 d
- Qualcomm · 29 open roles · median 92 d
- NVIDIA · 22 open roles · median 51 d
- NXP Semiconductors · 18 open roles · median 91 d
- Synopsys · 12 open roles · median 23 d
- Micron Technology · 11 open roles · median 63 d
How we counted: 246 open DFT Engineering (DFT Test) roles from 52 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.