Principal DFT Engineer - Austin, Texas, United States
$180,000 USD yearly
Originally posted 18 August 2026 by the employer.
SambaNova is looking for a Principal DFT Engineer to build RDU chips.
About the role
This role involves defining and implementing DFT architecture for RDU chips within the context of machine learning and artificial intelligence applications.
What you'll do
- Define and implement block-level and SoC-level DFT architecture for large, hierarchical SoCs.
- Develop and maintain ATPG flows for stuck-at, at-speed, and advanced fault models.
- Develop scripts and automation for DFT insertion, ATPG, coverage analysis, pattern generation, and debug.
- Generate production-quality ATPG and MBIST patterns and support deployment to ATE.
- Support silicon diagnosis, failure localization, yield analysis, and manufacturing test optimization.
- Develop and maintain JTAG, IEEE 1500, and IEEE 1687/IJTAG infrastructure for internal test and debug access.
What you'll need
- B.S. in computer science, computer engineering, or related field.
- 10+ years relevant industry experience.
- Deep understanding of scan insertion, scan compression, ATPG, MBIST, JTAG, and hierarchical DFT.
- Hands-on experience with Siemens Tessent tool flow or equivalent industry standard DFT tools.
- Strong understanding of advanced ATPG, silicon diagnosis, and failure localization methodologies.
- Experience with STA constraints and analysis for DFT modes and SDF simulations.
- Working knowledge of Verilog/System-Verilog simulators and waveform debugging.
Nice to have
- Experience with ATE pattern deployment and silicon bring-up.
- Experience with multi-die/chiplet DFT, known-good-die test, or die-to-die interface testing.
- Experience with large compute, AI accelerator, or HPC SoCs.
- Familiarity with cell-aware ATPG, small-delay defects, IEEE 1500, IEEE 1687/IJTAG, and low-power DFT.
This role has been open 59 days — slightly above the 57-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
242
|
Median days open
57 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (242 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 242 |
| Open roles in the wider Digital Design & Verification family | 7 | 3198 · 115 employers |
| Median days open | 59 d | 57 d (+2 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Who's hiring in this category
- AMD · 39 open roles · median 43 d
- NVIDIA · 23 open roles · median 35 d
- Qualcomm · 23 open roles · median 100 d
- NXP Semiconductors · 18 open roles · median 65 d
- Synopsys · 14 open roles · median 24 d
- Micron Technology · 10 open roles · median 64 d
How we counted: 242 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.