Principal DFT Engineer - Austin (Oakhill, Office), United States
Originally posted 10 June 2026 by the employer.
About the role
As a Principal DFT Engineer, you will handle DFT implementation and verification across subsystem- and top-level designs within the MCU & MPU Engineering & Design Enablement (MMEDE) business unit.
What you'll do
- Handle RTL design for DFT-related changes at both subsystem level and top level. - Insert MBIST RTL for memories and verify them. - Analyze scan DRCs and fix them in RTL. - Analyze ATPG reports on coverage, devise mechanisms to improve coverage, and generate patterns for ATE. - Insert TAP, IOs, and test pinmux using NXP DFT flows. - Bring up power-aware RTL and gate-level simulations (GLS), managing regression suites for ATPG and non-ATPG simulations. - Bring up patterns on wafer probe and final test in collaboration with product and test engineering teams.
What you'll need
- 5+ years of experience in DFT implementation and verification of scan architectures, JTAG, memory BIST, and ATPG. - Strong grounding in digital design concepts and RTL coding with Verilog or VHDL. - Experience with scan insertion, ATPG DRC, coverage analysis, and simulation debug with timing/SDF. - Demonstrated ability to debug and root cause simulation failures.
Skills: DFT implementation, MBIST, ATPG, Scan DRCs, JTAG
This role has been open 122 days — well above the 63-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
248
|
Median days open
63 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (248 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 248 |
| Open roles in the wider Digital Design & Verification family | 131 | 3298 · 115 employers |
| Median days open | 45 d | 63 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DFT implementation, MBIST, ATPG, Scan DRCs, JTAG
Who's hiring in this category
- AMD · 39 open roles · median 44 d
- Qualcomm · 25 open roles · median 77 d
- NVIDIA · 23 open roles · median 41 d
- NXP Semiconductors (this employer) · 19 open roles · median 46 d
- Synopsys · 15 open roles · median 29 d
- Intel Corporation · 10 open roles · median 63 d
How we counted: 248 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.