Principal Design Verification Engineer - San Jose, California, United States
$180,000 - $255,000 USD yearly
Originally posted 17 August 2026 by the employer.
RDU is the core of SambaNova's technology.
About the role
What you'll do
- Own verification end to end for a major subsystem of the RDU: test plan, testbench architecture, coverage model, and sign-off criteria. - Build the coverage model for your area, set the closure bar, and drive it to closure ahead of tape-out. - Develop testbench components, agents, checkers, and stimulus at block, full-chip, system, and gate level. - Serve as the technical authority for verification of your subsystem: review and arbitrate testbench design decisions, and lead debug on the hardest failures. - Verify functional and performance behavior. - Contribute to emulation and FPGA prototyping, and support silicon bring-up and post-silicon debug in the lab.
What you'll need
- BS or MS in EE, CS, or CE with 7+ years of industry experience in ASIC design verification. - Deep hands-on expertise in SystemVerilog and SVA with a standard methodology (UVM, OVM, or VMM), plus scripting in Python and C/C++. - Full-cycle DV ownership from test plan through tape-out on at least one complex ASIC or major subsystem, including owning a coverage model to closure. - Experience verifying digital logic in a CPU, GPU, SoC, or comparably complex ASIC. - Track record of debugging hard, intermittent, or low-reproducibility pre-silicon failures to root cause. - Working knowledge of modern computer architecture and of machine learning accelerators or SoCs.
Nice to have
- MS or PhD in EE, CS, or CE with 10+ years of experience in ASIC design verification. - Depth in high-speed I/O verification: protocol-level verification of PCIe or Ethernet, and memory subsystems such as HBM or DDR. - Performance verification methodology: building performance benches and analyzing results. - Formal verification and assertion-based methods. - Experience evaluating, integrating, and validating third-party verification IP. - Gate-level simulation and debug. - Emulation and FPGA prototyping platforms. - Post-silicon lab bring-up and functional validation, debugging first-silicon issues to root cause. - Fluency with Claude or other AI tools applied to verification and flow development.
Skills: SystemVerilog, UVM, test plan, coverage model, ASIC design verification, ML workloads
This role has been open 60 days — below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1205
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (1205 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1205 |
| Open roles in the wider Digital Design & Verification family | 7 | 3198 · 115 employers |
| Median days open | 59 d | 64 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: SystemVerilog, UVM, test plan, coverage model, ASIC design verification, ML workloads
Who's hiring in this category
- Qualcomm · 110 open roles · median 38 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 86 open roles · median 58 d
- Synopsys · 64 open roles · median 32 d
- SiFive · 55 open roles · median 74 d
- Cadence Design Systems · 50 open roles · median 116 d
How we counted: 1205 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.