Principal Design Verification Engineer, HBM - Richardson, TX, United States
Originally posted 15 August 2026 by the employer.
Work on HBM designs.
About the role
This role involves verifying IP, subsystem, full-chip, and system-level HBM and DRAM designs to ensure functional correctness, performance, power efficiency, and product quality.
What you'll do
- Verify IP, subsystem, full-chip, and system-level HBM and DRAM designs.
- Develop comprehensive verification plans from architecture and functional specifications.
- Create, enhance, and maintain verification environments, UVM testbenches, test suites, and automated regression infrastructures.
- Define and execute coverage-driven verification strategies to achieve functional, assertion, and code coverage goals.
- Lead debug and root-cause analysis of complex design issues and drive bug resolution.
- Apply advanced digital and mixed-signal verification methodologies using industry-standard simulation and verification tools.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
- 10+ years of experience in digital and/or mixed-signal design verification.
- Strong understanding of CMOS circuit design fundamentals.
- Strong expertise in SystemVerilog, UVM, assertion-based verification (SVA), and coverage-driven verification methodologies.
- Experience debugging complex design and verification issues in large-scale ASIC, SoC, or memory designs.
- Proficiency and experience in AI assisted verification flow.
Nice to have
- Strong understanding or experience in DRAM and/or HBM architecture, protocol operation, memory subsystems, and high-performance computing applications.
- Experience with analog and digital simulation tools such as HSPICE, FineSim, Verilog, and mixed-signal simulation environments.
- Proficiency in Python, Perl, or similar scripting languages for verification automation, regression management, and data analysis.
- Experience developing scalable verification infrastructures and automation frameworks for complex SoC or memory products.
Skills: HBM designs, UVM testbenches, SystemVerilog, coverage-driven verification, silicon products
This role has been open 62 days — below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1205
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (1205 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 42 | 1205 |
| Open roles in the wider Digital Design & Verification family | 103 | 3198 · 115 employers |
| Median days open | 80 d | 64 d (+16 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: HBM designs, UVM testbenches, SystemVerilog, coverage-driven verification, silicon products
Who's hiring in this category
- Qualcomm · 110 open roles · median 38 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 86 open roles · median 58 d
- Synopsys · 64 open roles · median 32 d
- SiFive · 55 open roles · median 74 d
- Cadence Design Systems · 50 open roles · median 116 d
How we counted: 1205 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.