Principal Design Verification Engineer - Bengaluru, Karnataka, India
Originally posted 27 August 2026 by the employer.
About the role
This role involves the functional verification of designs, encompassing block-level and system-level verification plans, test execution, and coverage closure. This position focuses on purpose-built connectivity solutions for rack-scale AI infrastructure, integrating CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
What you'll do
- Develop and execute block-level and system-level verification plans.
- Write and execute test sequences and collect and close coverage.
- Collaborate with RTL designers to debug failures and refine verification processes.
- Utilize coding and protocol expertise to contribute to functional verification.
- Develop user-controlled random constraints in transaction-based verification methodologies.
- Write assertions, cover properties, and analyze coverage data.
- Create VIP abstraction layers for sequences to simplify and scale verification deployments.
What you'll need
- Minimum of 12 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications.
- Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor’s degree required).
- Knowledge of industry-standard simulators, revision control systems, and regression systems.
- Experience interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments.
- Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above.
- Ability to independently develop test plans and sequences in UVM to generate stimuli.
- Experience writing assertions, cover properties, and analyzing coverage data.
- Developing VIP abstraction layers for sequences to simplify and scale verification deployments.
Nice to have
- Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC.
- Experience with buffering and queuing with QoS on complex NOC-based SoCs.
- Analyzing performance at the system level on switching fabrics.
Skills: functional verification, PCIe/CXL, UVM, test sequences, coverage closure, assertions
This role has been open 31 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1157
|
Median days open
63 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1157 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 1157 |
| Open roles in the wider Digital Design & Verification family | 54 | 3077 · 114 employers |
| Median days open | 65 d | 63 d (+2 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: functional verification, PCIe/CXL, UVM, test sequences, coverage closure, assertions
Who's hiring in this category
- AMD · 101 open roles · median 38 d
- Qualcomm · 97 open roles · median 52 d
- NVIDIA · 85 open roles · median 70 d
- Synopsys · 65 open roles · median 23 d
- SiFive · 56 open roles · median 55 d
- NXP Semiconductors · 51 open roles · median 81 d
How we counted: 1157 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.