Principal Design Engineer - United States
Originally posted 28 August 2026 by the employer.
About the role
This role involves contributing to the development of complex, high-performance semiconductor designs, developing and integrating RTL for advanced SoCs and silicon platforms.
What you'll do
- Design, implement, and integrate high-quality synthesizable RTL using SystemVerilog.
- Translate architectural specifications into robust, efficient microarchitectures and RTL implementations.
- Develop RTL that meets requirements for performance, power, area, and functionality.
- Develop and maintain unit-level and block-level test environments in collaboration with verification engineers.
- Debug functional issues using simulation, waveform analysis, assertions, and other verification tools.
- Collaborate with physical design engineers to understand and address timing, area, power, and implementation constraints.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
- 10+ years of relevant RTL/ASIC design experience.
- Proficiency in Verilog or SystemVerilog.
- Understanding of digital logic design and synchronous design principles.
- Experience developing synthesizable RTL for ASIC or FPGA implementations.
- Familiarity with simulation and RTL debugging.
- Understanding of common SoC interfaces and protocols.
- Basic understanding of synthesis, timing, and physical implementation considerations.
Skills: synthesizable RTL, SystemVerilog, microarchitectures, simulation, synthesis
This role has been open 50 days — well below the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1037
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (1037 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 1037 |
| Open roles in the wider Digital Design & Verification family | 123 | 3202 · 115 employers |
| Median days open | 52 d | 60 d (−8 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: synthesizable RTL, SystemVerilog, microarchitectures, simulation, synthesis
Who's hiring in this category
- Qualcomm · 140 open roles · median 64 d
- Synopsys · 86 open roles · median 32 d
- AMD · 71 open roles · median 38 d
- Analog Devices · 47 open roles · median 50 d
- NVIDIA · 44 open roles · median 60 d
- NXP Semiconductors · 42 open roles · median 86 d
How we counted: 1037 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.