Principal Design Engineer – High-Speed Interconnect - Austin, Texas, United States
$249,900 - $338,100 USD yearly
Originally posted 20 July 2026 by the employer.
About the role
Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems, including PCIe, CXL, and UALink, across multiple silicon products.
What you'll do
- Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, register definitions, and synthesizable RTL. - Drive the development process from concept through RTL creation, subsystem integration, verification support, synthesis preparation, and final delivery. - Collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet functionality, bandwidth, latency, power, area, and timing targets. - Analyze traffic patterns, workloads, queue depths, credits, outstanding transactions, and buffer requirements to guide implementation tradeoffs. - Lead technical reviews, debug cross-functional issues, improve building methodologies, and mentor engineers.
What you'll need
- 8+ years of experience in RTL build, microarchitecture, subsystem integration, or related semiconductor roles. - Deep hands-on expertise in SystemVerilog and the development of sophisticated, high-performance digital subsystems. - Deep understanding of PCIe, CXL, and UALink, covering transaction flows, ordering, flow control, retries, error handling, host/device integration, memory expansion, and coherent connectivity. - Experience with coherent or non-coherent interconnects, cache hierarchies, memory systems, and high-speed I/O subsystems. - Strong understanding of AXI, CHI, ACE, APB, streaming interfaces, buffering, arbitration, scheduling, and backpressure. - Experience with CDC, RDC, reset sequencing, low-power build, lint, X-propagation, formal verification, synthesis, timing analysis, and waveform debug. - Bachelor’s or Master’s degree, or equivalent experience, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Nice to have
- Experience with PCIe Gen6 or later, CXL 2.0 or later, UALink, chiplets, or die-to-die connectivity. - Knowledge of RAS, IDE, TDISP, security, memory pooling, CXL.cache, CXL.mem, and accelerator connectivity. - Experience integrating third-party IP, PHYs, firmware-visible capabilities, PCIe configuration space, BARs, interrupts, and error-management features. - Validated experience in delivering sophisticated RTL or subsystem builds on schedule and meeting functional, performance, power, area, and quality targets.
Skills: RTL build, microarchitecture, SystemVerilog, PCIe, CXL, UALink
This role has been open 90 days — well above the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1036
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (1036 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 23 | 1036 |
| Open roles in the wider Digital Design & Verification family | 104 | 3224 · 116 employers |
| Median days open | 105 d | 61 d (+44 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL build, microarchitecture, SystemVerilog, PCIe, CXL, UALink
Who's hiring in this category
- Qualcomm · 140 open roles · median 65 d
- Synopsys · 86 open roles · median 33 d
- AMD · 71 open roles · median 39 d
- Analog Devices · 47 open roles · median 51 d
- NVIDIA · 42 open roles · median 61 d
- NXP Semiconductors · 42 open roles · median 87 d
How we counted: 1036 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.