Principal Design Engineer - Bangalore, India
Originally posted 8 June 2026 by the employer — open 94 days.
About the role
This Principal Design Engineer role involves taking a key position on the Analog and Mixed signal design team within a Die to Die Product Development Team, focusing on High Speed D2D and SERDES products.
What you'll do
- Design and develop analog/mixed signal IC circuit blocks from initial concept/specification through final verification.
- Work closely with Layout Design Engineers on IC circuit blocks and PMA sections.
- Collaborate with Technical Team Leads on circuit design and SERDES architectures.
- Work with global teams across different time zones.
What you'll need
- Minimum 8 years of CMOS design experience, preferably in CMOS SERDES or high-speed I/O IC design.
- Good understanding of jitter and signal equalization techniques.
- Design experience in SERDES circuit blocks such as Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators.
- Proficiency in using CAD tools for circuit simulation, layout, and physical verification.
Skills: D2D and SERDES products, high speed I/O, FinFET CMOS, jitter, signal equalization
This role has been open 93 days — slightly above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 19 | 217 |
| Median days open | 153 d | 91 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: D2D and SERDES products, high speed I/O, FinFET CMOS, jitter, signal equalization
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems (this employer) · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.