Principal Design Engineer - Hyderabad, India
Originally posted 4 September 2026 by the employer — open 6 days.
This role focuses on UCIe, D2D, PCIe, DDR/LPDDR, HBM, GDDR, and SerDes IPs.
About the role
This role involves the architecture, design, and delivery of high-speed Analog/Mixed-Signal IPs and subsystems.
What you'll do
- Architect, design, and deliver high-speed Analog/Mixed-Signal IPs and subsystems.
- Drive design closure for TX/RX, PLL, DLL, CDR, Clocking, Datapath, I/O, and interface circuits.
- Lead complex IP programs involving cross-functional teams including Analog Design, Layout, AMS Verification, Digital, and Physical Design.
- Mentor engineers and drive technical excellence, innovation, and execution.
- Lead project execution, staffing, risk management, and customer engagements for management roles.
What you'll need
- Strong expertise in high-speed interface design: UCIe / Die-to-Die (D2D), PCIe Gen3/4/5/6, DDRx / LPDDRx / GDDRx / HBM, High-speed SerDes architectures.
- Strong Analog Design and I/O fundamentals.
- Knowledge of SI/PI, ESD, Reliability, Jitter, Timing, and PPA optimization.
- Experience delivering complex IPs from architecture to silicon.
- Excellent communication, leadership, and problem-solving skills.
Nice to have
- Experience with advanced technology nodes (16nm, 12nm, 10nm, 7nm, 5nm, 3nm).
- Experience in IP architecture, technology migration, and design reuse methodologies.
- Proven track record of leading large technical teams and delivering high-performance connectivity or memory interface solutions.
Skills: high-speed Analog/Mixed-Signal IPs, TX/RX, PLL, DDRx, PCIe Gen3/4/5/6, SerDes architectures
This role has been open 6 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 28 | 1317 · 100 employers |
| Median days open | 153 d | 91 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: high-speed Analog/Mixed-Signal IPs, TX/RX, PLL, DDRx, PCIe Gen3/4/5/6, SerDes architectures
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems (this employer) · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.