Principal Design Engineer - Austin, United States
Originally posted 7 May 2026 by the employer.
About the role
Cadence is seeking a Principal Design Engineer to handle subsystem and SOC level design verification. This role focuses on architecting SV-UVM testbenches and verifying ARM based designs through silicon realization.
What you'll do
- Independently handle verification of complex modules or own significant subsystem and SOC based verification components. - Define verification methodology, architecture, and verification strategy for scalable verification environments from scratch. - Develop verification test plans, code test cases, and execute debug to achieve functional coverage and code coverage goals. - Develop C based testcases and verify designs incorporating AMBA protocols. - Mentor and coach junior engineers to build their independent verification capabilities. - Work closely with cross-functional stakeholders across architecture, design, and internal and external customers.
What you'll need
- Experience working on subsystem and SOC level verification projects leading to silicon realization. - Experience in ARM based designs. - In-depth knowledge of SV-UVM and expertise in architecting scalable verification environments from scratch. - Experience in C based testcase development. - Strong knowledge of AMBA protocols including AXI, ACE, APB, and AHB. - Knowledge of at least one protocol among USB, PCIE, Ethernet, DDR, or LPDDR. - Experience in mentoring junior engineers.
Nice to have
- Prior experience with Cadence tools, flows, and verification tools. - Familiarity with ARM/CPU architectures. - Experience in developing C-based test cases for SOC verification and embedded C code development and debug. - Experience with assembly language programming. - Knowledge of protocols including UART, I2C, SPI, or JTAG. - Formal verification experience.
Skills: SV UVM, testbenches, functional coverage, code coverage, AMBA protocols
This role has been open 170 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1259
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (1259 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 52 | 1259 |
| Open roles in the wider Digital Design & Verification family | 123 | 3328 · 115 employers |
| Median days open | 123 d | 65 d (+58 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SV UVM, testbenches, functional coverage, code coverage, AMBA protocols
Who's hiring in this category
- Qualcomm · 120 open roles · median 44 d
- NVIDIA · 93 open roles · median 65 d
- AMD · 92 open roles · median 54 d
- Synopsys · 65 open roles · median 40 d
- SiFive · 55 open roles · median 82 d
- Cadence Design Systems (this employer) · 52 open roles · median 124 d
How we counted: 1259 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.