Principal Design Engineer
$185,000 USD yearly
Originally posted 5 October 2026 by the employer.
About the role
As a Principal Design Engineer, you will develop micro-architecture and implement front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers.
What you'll do
- Own full chip or block level design from architecture to GDS, driving multiple complex designs to production.
- Execute front-end design flows including architecture, RTL, simulations, synthesis, timing closure, gate-level simulations (GLS), and DFT.
- Implement design for test (DFT), including stuck-at and transition scan test insertion.
- Support silicon bring-up and debug across small-geometry CMOS (≤28nm) processes.
- Collaborate with verification teams using UVM-based design verification environments.
What you'll need
- Bachelor’s degree in Electrical Engineering (EE).
- 8+ years of experience supporting or developing complex SoC or silicon products for Switch ASIC, networking applications, server, or storage.
- Hands-on knowledge of high-speed communication and interface protocols such as PCIe (Gen-3 and above), Ualink, Esun, and Ethernet.
- Experience with Synopsys or Cadence digital design tools and flows.
- Proven expertise in silicon bring-up, debug, and small-geometry CMOS (≤28nm) design.
- Authorization to work in the US.
Nice to have
- Firmware development with C-language, or scripting with Python or equivalent programming languages.
- Development or support experience with PCIe or Ethernet Switch products.
- Master’s degree in Electrical Engineering.
More semiconductor jobs: Astera Labs jobs · RTL design jobs · San Jose jobs
This role has been open 30 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1086
|
Median days open
61 d
|
Category median salary (all employers)
$188k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1086 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 1086 |
| Open roles in the wider Digital Design & Verification family | 66 | 3488 · 119 employers |
| Median days open | 51 d | 61 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Who's hiring in this category
- Qualcomm · 142 open roles · median 71 d
- Synopsys · 90 open roles · median 48 d
- AMD · 78 open roles · median 47 d
- NXP Semiconductors · 45 open roles · median 104 d
- NVIDIA · 44 open roles · median 61 d
- Analog Devices · 41 open roles · median 51 d
How we counted: 1086 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.