Principal Design Engineer - CORK 01, Ireland
Originally posted 13 August 2026 by the employer.
About the role
This role involves taking a technical leadership position on the PMA design team as part of a SERDES Product Team. You will focus on the design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on 5nm FinFET CMOS technology nodes.
What you'll do
- Design High Speed SERDES products at data rates up to and exceeding 112 Gbps on FinFET CMOS technology nodes.
- Design and develop analog/mixed signal IC circuit blocks from initial concept through final verification.
- Collaborate with Physical Design Engineers on IC circuit blocks and PMA sections.
- Provide technical leadership in circuit design and SERDES architectures.
- Work with global teams across different time zones.
What you'll need
- Minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC design and development.
- BEng, MEng or PhD qualification.
- Working knowledge of common SERDES standards and their electrical requirements.
- Thorough understanding of jitter and signal equalization techniques.
- Proficient design experience in SERDES circuit blocks such as Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators.
Skills: High Speed SERDES, 112 Gbps, FinFET CMOS, jitter, signal equalization
This role has been open 47 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 29 | 1385 · 107 employers |
| Median days open | 181 d | 76 d (+105 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: High Speed SERDES, 112 Gbps, FinFET CMOS, jitter, signal equalization
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems (this employer) · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.