Principal Design Automation Engineer - San Jose, CA, United States
$176,000 - $298,000 USD yearly
Originally posted 23 July 2026 by the employer.
About the role
As a Principal Design Automation Engineer in the NVE Design Engineering organization at Micron Technology, you will support NAND circuit development through design automation, agentic circuit-design enablement, and environment transition.
What you'll do
- Implement core Xpath, Ypath, and Array design during project execution, integrate core schematics into full-chip schematics, and validate functionality via block- and chip-level simulations using standard industry simulators. - Implement analog and mixed-signal circuit design including charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap references, LDOs, thermometers, page buffers, PDNs, and level shifters. - Develop and productize agentic enablement for circuit design, including AI/LLM-assisted flows for environment setup, self-healing configuration, guided simulation and debug, and intelligent corner planning. - Create automated schematic and layout checks, review assistance tools, and documentation synthesis workflows for analog/mixed-signal verification, golden reference management, and regression gating. - Serve as a technical authority across analog and core teams to solve issues at the intersection of circuit behavior, modeling, simulation methodology, and automation reliability. - Partner with circuit designers, firmware, validation, and architecture teams to integrate tooling into project execution and achieve measurable cycle-time reduction.
What you'll need
- MS in Electrical Engineering (or related field) and 8+ years of relevant NAND design experience, including proficient knowledge of NAND Flash memory read, program, and erase algorithms. - Proficiency in analog and mixed-signal circuit design and layout for components such as page buffers, block selectors, Xdecoders, Ydecoders, bias tables, charge pumps, op amps, DACs, ADCs, and PDNs. - Strong grounding in semiconductor and device physics, including understanding of reliability issues such as CHC, NBTI, stress, snapback, Electromigration (EM), and IR analysis. - Demonstrated experience in circuit verification flows, layout planning, parasitic extraction, PVT/mismatch analysis, and simulators including HSPICE, Fast SPICE, and Verilog. - Proven proficiency in Python for engineering automation, including maintainable scripts, libraries, or frameworks interfacing with EDA tools for simulation control, data extraction, and regression management. - Proficiency with Cadence design tools, LVS/DRC verification tools, and UNIX environments.
Nice to have
- PhD in Electrical Engineering.
Skills: design automation, agentic circuit-design enablement, AI/LLM-assisted flows, NAND design, analog mixed-signal circuit design
This role has been open 87 days — well above the 74-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
671
|
Median days open
74 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (671 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 45 | 671 |
| Open roles in the wider Physical Implementation family | 77 | 1441 · 109 employers |
| Median days open | 48 d | 74 d (−26 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: design automation, agentic circuit-design enablement, AI/LLM-assisted flows, NAND design, analog mixed-signal circuit design
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 171 d
- Synopsys · 63 open roles · median 37 d
- Micron Technology (this employer) · 44 open roles · median 48 d
- Qualcomm · 36 open roles · median 76 d
- GlobalFoundries · 33 open roles · median 39 d
- Keysight Technologies · 32 open roles · median 73 d
How we counted: 671 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.