$216,600 - $325,000 USD yearly
Originally posted 13 October 2026 by the employer.
About the role
As a Principal CPU PPA Pathfinding Engineer, you will analyze, define, and evaluate power, performance, and area options for future Qualcomm CPU projects. You will translate architectural concepts, process technology choices, design methodologies, and physical design constraints into PPA projections and recommendations.
What you'll do
- Lead CPU PPA pathfinding studies from early concept exploration through implementation feasibility assessment.
- Define and compare PPA options across CPU microarchitecture, frequency targets, process technology, standard-cell libraries, voltage operating points, floorplans, clocking strategies, and implementation methodologies.
- Build representative implementation experiments and design-of-experiment frameworks to quantify trade-offs and evaluate iso-power, iso-performance, and iso-area operating points.
- Generate area and power estimates, frequency projections, and power-performance curves across representative CPU workloads and thermal constraints.
- Partner with CPU Architecture, RTL, Performance, Power, Circuits, Physical Design, CAD, Process Technology, SoC, and Product teams to align implementation assumptions.
- Own competitive CPU PPA analysis across product segments using benchmark results, performance-per-area metrics, die analysis, and silicon measurements.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 8+ years of engineering experience (or Master's with 7+ years, or PhD with 6+ years).
- 15 years of relevant industry experience in CPU or high-performance ASIC/SoC implementation.
- Hands-on implementation background spanning physical synthesis, floorplanning, place and route, clock tree synthesis, static timing analysis, power analysis, and signoff.
- Experience evaluating and optimizing power, performance, and area for high-frequency CPU cores or complex designs.
- Understanding of CPU implementation trade-offs, critical paths, physical constraints, low-power techniques, and advanced-node design challenges.
- Proficiency in scripting and automation using Python, Tcl, Perl, or similar languages.
Nice to have
- Experience with CPU microarchitecture and performance analysis, including workload, critical path, frequency, power, and area trade-offs.
- Experience with advanced process nodes, technology pathfinding, standard-cell libraries, voltage, interconnect, and physical design trade-offs.
- Hands-on experience with industry-standard implementation and signoff tools from Cadence and/or Synopsys.
- Experience developing PPA estimation models, power-performance curves, design dashboards, or automated experiment frameworks.
- Knowledge of power modeling, thermal constraints, multiple power domains, UPF-based implementation, and low-power optimization techniques.
- Experience with pre-silicon to post-silicon PPA correlation or silicon characterization.
Skills: PPA pathfinding, place and route, static timing analysis, floorplanning, power-performance curves, CPU implementation
More semiconductor jobs: Qualcomm jobs · Physical design jobs · San Diego jobs
First seen in our index 30 days ago, well below the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
741
|
Median days since first seen
63 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (741 roles · 90 employers) |
|---|---|---|
| Open roles in this specialty | 115 | 741 |
| Open roles in the wider Physical Implementation family | 164 | 1676 · 120 employers |
| Median days since first seen | 63 d | 63 d (same as this employer) |
| Median salary (USD postings) | n/a | $187k |
Skills observed across this category: PPA pathfinding, place and route, static timing analysis, floorplanning, power-performance curves, CPU implementation
Who's hiring in this category
- Qualcomm (this employer) · 115 open roles · median 64 d
- AMD · 64 open roles · median 45 d
- Broadcom · 47 open roles · median 24 d
- NVIDIA · 46 open roles · median 84 d
- Synopsys · 45 open roles · median 42 d
- Apple · 32 open roles · median 7 d
How we counted: 741 open Physical Design (Physical Design) roles from 90 employers tracked in the SemiconductorJobs index, counted 13 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Physical Implementation family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.