Principal Competitive CPU Microarchitecture & Platform Performance Engineer - TX, Home Office, United States
Originally posted 18 September 2026 by the employer — open 1 day.
About the role
This role focuses on building workload-relevant models of future AMD and competitor server platforms before silicon is available. The work involves explaining what a platform is likely to deliver on real workloads, why, and with what level of confidence.
What you'll do
- Develop comparative models of CPU front ends, execution resources, branch behavior, cache and TLB hierarchies, coherence, memory subsystems, and multi-socket or NUMA behavior.
- Model platform constraints including memory bandwidth and capacity, DDR or HBM attachment, PCIe, CXL, networking, storage paths, power limits, and thermals.
- Translate incomplete roadmap disclosures into explicit assumptions with confidence levels, alternate cases, and sensitivity ranges.
- Use measured silicon, performance counters, and platform telemetry to calibrate models and identify failing assumptions.
- Perform bottleneck decomposition to explain why a workload favors AMD or a competitor and which architectural mechanism is responsible.
- Create architecture diagrams, technical narratives, and executive-ready content that clearly show causes, risks, and areas of AMD advantage.
What you'll need
- Deep hands-on experience in CPU microarchitecture, silicon performance, system architecture, or performance modeling.
- Strong knowledge of out-of-order pipelines, branch prediction, fetch and decode, execution back ends, and simultaneous multithreading behavior.
- Expertise in cache, TLB, coherence, prefetching, memory controllers, NUMA, bandwidth, latency, and capacity scaling.
- Experience with hardware performance counters, profiling tools, microbenchmarks, system telemetry, and bottleneck analysis.
- Strong quantitative and scripting or data-analysis skills used in performance investigations.
- Ability to reason from incomplete information, make assumptions explicit, and show which unknowns can change the conclusion.
Nice to have
- Pre-silicon performance modeling, architecture exploration, or simulation experience.
- Hands-on analysis of more than one server CPU architecture or ISA.
- Experience with memory-intensive workloads, virtualization, HPC, analytics, or CPU-side AI workloads.
- Familiarity with power modeling, thermals, platform firmware, and frequency or power-management behavior.
- Experience evaluating vendor disclosures, patents, conference presentations, or public technical materials under clean-room rules.
This role has been open 1 day — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
938
|
Median days open
61 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (938 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 61 | 938 |
| Open roles in the wider Digital Design & Verification family | 250 | 3011 · 114 employers |
| Median days open | 61 d | 61 d (same as this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Qualcomm · 143 open roles · median 53 d
- AMD (this employer) · 61 open roles · median 61 d
- Synopsys · 57 open roles · median 29 d
- NXP Semiconductors · 51 open roles · median 67 d
- NVIDIA · 48 open roles · median 44 d
- Analog Devices · 39 open roles · median 73 d
How we counted: 938 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.