Principal Chip Lead, Silicon Co-Design Group - CA, Santa Clara, United States
$232,000 - $368,000 USD yearly
Originally posted 27 July 2026 by the employer.
About the role
This role involves serving as the technical lead for silicon programs within the Silicon Co-Design Group, guiding co-design feature integration and resolving multi-functional bugs.
What you'll do
- Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs.
- Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution.
- Help resolve multi-functional bugs by translating ambiguous symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging.
- Steward the qualification playbook, guiding mitigations and capturing lessons as reusable methodology.
- Shape the program’s technical narrative by surfacing key risks, trade-offs, and mitigations as decision-ready options for executive leadership.
- Lead the program’s Critical Debug and SCG Technical Execution forums, and represent the chip externally with early insight into technical risks.
What you'll need
- BS or MS in Electrical or Computer Engineering, plus over a decade of proven track record in post-silicon bring-up, validation, or system integration leadership at a major semiconductor company, including work on multiple shipped silicon products.
- 15+ years of experience.
- Strong end-to-end understanding of SoC and ASIC architecture, with recognized expertise in at least one subsystem such as HBM, SerDes, power and thermal, or packaging.
- Specific examples of silicon-level impact, such as faster bring-up, fewer escapes, yield recovery, or methodology contributions, especially turning ambiguous, multi-team failure modes into root-cause closure with reusable workarounds and write-ups.
- A track record of guiding technical decisions across functional boundaries without direct reporting authority, and translating sophisticated silicon issues into clear options for executive audiences.
Nice to have
- Prior experience as a Chip Lead, Project Tech Lead, or Principal or Distinguished Engineer on a flagship GPU, AI accelerator, CPU, networking ASIC, or other large SoC.
- Patents, conference papers, invited talks, or recognized contributions to silicon validation, post-silicon debug, or co-design integration.
- A history of building and sharing technical methodology beyond a single program — reusable playbooks, debug frameworks, or standards adopted by other teams.
- Hands-on debug experience with HBM, high-speed I/O, power and thermal, or packaging.
Skills: silicon programs, technical lead, multi-functional bugs, HBM, power and thermal, high-speed I/O
This role has been open 82 days — well above the 47-day median for Technical Program Management roles.
Technical Program Management · SOC Architecture
|
Open roles in category
175
|
Median days open
47 d
|
Median salary
$220k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (175 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 175 |
| Median days open | 33 d | 47 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $220k |
Skills observed across this category: silicon programs, technical lead, multi-functional bugs, HBM, power and thermal, high-speed I/O
Who's hiring in this category
- Qualcomm · 25 open roles · median 47 d
- NVIDIA (this employer) · 20 open roles · median 35 d
- AMD · 19 open roles · median 26 d
- Synopsys · 14 open roles · median 47 d
- Arm Holdings · 10 open roles · median 84 d
- Astera Labs · 6 open roles · median 68 d
How we counted: 175 open Technical Program Management (SOC Architecture) roles from 49 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.