Principal ASIC Design Engineer - United States

Originally posted 24 September 2026 by the employer.

About the role

This role involves owning the RTL design and micro-architecture of digital blocks for high-speed interface technologies. The position focuses on silicon-based validation of novel PHY solutions.

What you'll do

• Own the micro-architecture and RTL implementation of digital soft IP blocks (CSR/register file, clocking control logic, management bus interfaces, control state machines) in synthesizable SystemVerilog.
• Define and document block-level architecture specifications and interface control documents.
• Execute logic synthesis (Synopsys Design Compiler or Cadence Genus) and drive optimization toward PPA targets.
• Develop and maintain block-level SDC constraints; execute and close static timing analysis (PrimeTime or Tempus) across required corners and modes.
• Serve as the primary digital interface to the layout and implementation team, providing synthesized netlists, SDC constraints, floorplan guidance, and design intent documentation.
• Self-verify RTL through block-level simulation (VCS or Xcelium), waveform debug (Verdi or DVE), and directed testing.

What you'll need

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 7–12 years of ASIC design experience with at least one complete front-to-back tape-out.
• Proficiency in synthesizable SystemVerilog RTL design.
• Hands-on experience with logic synthesis (Design Compiler or Genus) and static timing analysis (PrimeTime or Tempus).
• Proficiency with RTL simulation and debug tools (VCS or Xcelium; Verdi or DVE) for block-level self-verification.
• Solid understanding of CDC analysis methodologies (SpyGlass, JasperGold CDC, or equivalent).
• Ability to work effectively at the interface between digital design and custom/analog implementation teams.
• Proficiency in leveraging AI tools for productivity across design, debug, and documentation workflows.

Nice to have

• Experience working within a custom mixed-signal design team.
• Hands-on experience with place-and-route (Cadence Innovus or equivalent) and physical verification sign-off (Mentor Calibre).
• Experience with mixed-signal or PHY-adjacent chip implementation.
• Familiarity with high-speed PHY architectures (SerDes, DDR, or equivalent).
• Familiarity with digital infrastructure for observability and silicon characterization.
• Familiarity with I2C management bus, Eye Monitor control logic, or PRBS-based error counting.
• Familiarity with DFT methodologies — scan insertion, ATPG planning, boundary scan.
• Experience with GLS flows using Liberty models and SPF parasitics.
• Familiarity with formal property verification (JasperGold or VC Formal).
• Prior experience in a small team or startup-like environment.

Skills: RTL design, micro-architecture, SystemVerilog, logic synthesis, static timing analysis, DFT