Principal ASIC Architect - Sunnyvale, CA, United States
Originally posted 2 April 2026 by the employer.
About the role
As a Principal ASIC Architect, you will lead all phases of ASIC architecture definition and design of processors for generative AI inference acceleration. This includes high-level silicon architecture planning and prototyping for multi-chip silicon solutions incorporating RISC-V cores, HBM, and PCIe connectivity.
What you'll do
- Lead architectural planning and definition of AI processors containing floating point AI compute cores, embedded memory, embedded RISC-V CPU cores, chip-to-chip networking fabric, HBM, and PCIe connectivity. - Propose chip design solutions, write detailed design specifications, lead architectural modeling, and define ASIC development milestones across functionality, performance, accuracy, power efficiency, and manufacturability. - Collaborate with ASIC design, design verification, SOC physical design, and software teams, providing technical guidance, leading design reviews, and mentoring engineers. - Evaluate new silicon IP technologies, EDA tools, and methodologies to support product execution and chip design efficiency.
What you'll need
- 15+ years of hands-on experience in silicon design engineering and architectural planning of high-performance compute processors (such as GPUs, CPUs, or TPUs), HBM, and high-speed SerDes networking technologies for AI workloads. - Demonstrated understanding of generative AI algorithms, attention mechanisms, foundation transformer models, and mapping these functions to hardware. - Strong Verilog programming skills, with hands-on experience in RTL verification, performance modeling, performance analysis, debugging, and optimization. - Proven track record of developing architectural C-models, SystemC, or TLM, with expert-level proficiency in C/C++ and scripting via Python or Perl. - MS or PhD in Electrical Engineering, Computer Engineering, or a related engineering discipline.
Skills: ASIC architecture, AI processors, silicon architecture planning, microarchitecture, HBM, PCIe
This role has been open 119 days — well above the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
479
|
Median days open
76 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tensordyne | All employers we track in this specialty (479 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 479 |
| Open roles in the wider Digital Design & Verification family | 3 | 3298 · 115 employers |
| Median days open | 119 d | 76 d (+43 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: ASIC architecture, AI processors, silicon architecture planning, microarchitecture, HBM, PCIe
Who's hiring in this category
- Qualcomm · 79 open roles · median 85 d
- NVIDIA · 54 open roles · median 71 d
- Apple · 38 open roles · median 14 d
- AMD · 35 open roles · median 71 d
- Arm Holdings · 27 open roles · median 119 d
- Micron Technology · 22 open roles · median 111 d
How we counted: 479 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.